On-Die Logic Analyzer for SoC Debugging
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Solution Overview
Problem
The increasing complexity of silicon designs and multi-chip integration in system-on-chip (SoC) implementations makes post-silicon debugging challenging, especially due to hidden interconnects and the high cost of using external logic analyzers to capture high-frequency signals, which limits debugging to vendor sites.
Innovation Solution
An on-die logic analyzer (ODLA) is implemented to collect and capture internal signals on a unidirectional front side bus, providing visibility into processor-chipset interconnects and enabling precise data capture and analysis, with features like trigger control and dynamic queue combining to optimize storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external logic analyzers are used to capture high-frequency signals, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent embeds a logic analyzer directly within the semiconductor die, nesting the debugging instrument inside the device under test. This eliminates the need for external logic analyzers and their associated complex connections, while maintaining the ability to capture high-frequency internal signals with high precision.
Solution Approach 2:
The patent introduces an on-die logic analyzer as an intermediary component that captures internal signals directly at the source. This mediator enables precise measurement of high-frequency signals without requiring complex external equipment, simplifying the overall debugging system while maintaining measurement accuracy.
2Adaptability or versatility
If more transistors are integrated on the silicon die, then functionality is improved, but debugging difficulty increases
Solution Approach 1:
The patent segments the debugging function by placing dedicated logic analyzer resources directly on the silicon die, separate from the main functional transistors. This segmentation allows the increased transistor count for functionality to coexist with embedded debugging capabilities, making it easier to detect and measure signals in complex high-functionality systems.
3Area of stationary object
If system-on-chip integration is increased to reduce form factor, then compactness is improved, but interconnect visibility for debugging deteriorates
Solution Approach 1:
The patent nests the logic analyzer within the system-on-chip structure, allowing it to access and capture signals from internal interconnects that would otherwise be invisible to external debugging tools. This nesting maintains compact form factor while preventing information loss by providing direct visibility into hidden interconnect signals.
Data Source
AI summary
In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.