On-Die Logic Analyzer for Memory Timing Validation
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Solution Overview
Problem
Debugging memory systems is complicated by inefficient command bus timings and improper command bus protocols, which can lead to errors and reduced bandwidth, and external measurement equipment cannot accurately measure in-system timing values, especially at high speeds with features like DFE or CTLE.
Innovation Solution
An on-die logic analyzer (ODLA) is integrated into memory devices to measure and validate command sequence timings without introducing invasive components, allowing for efficient debugging and validation of command-to-command timings within the memory system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external measurement equipment is used to measure command bus timings, then measurement capability is provided, but measurement precision deteriorates at high speeds with DFE or CTLE features
Solution Approach 1:
The patent introduces an on-die logic analyzer as an intermediary measurement device integrated within the memory die. This mediator captures command bus timing signals internally using dedicated timing analysis circuitry, enabling accurate measurement of in-system timing values including DFE and CTLE features without requiring external equipment that cannot properly measure these high-speed characteristics.
Solution Approach 2:
The patent replaces external mechanical measurement systems (oscilloscopes, logic analyzers) with an integrated electronic timing analysis system built into the memory die. The on-die logic analyzer uses electronic circuitry including timing counters, state machines, and memory elements to capture and store timing information, substituting the need for external measurement equipment that cannot accurately measure high-speed in-system timings.
2Measurement precision
If invasive components are introduced for measurement, then measurement capability is improved, but signal integrity deteriorates
Solution Approach 1:
The patent merges the measurement functionality with the existing memory die structure by integrating the on-die logic analyzer directly into the device. The timing analysis circuitry is combined with the memory controller and command bus infrastructure, allowing measurement of command timings without introducing separate invasive components that would disrupt signal integrity. The measurement function shares the same physical and electrical environment as the normal memory operations.
3Productivity
If debugging time is reduced, then productivity is improved, but measurement precision may deteriorate without proper equipment
Solution Approach 1:
The patent implements self-service by enabling the memory device to measure and analyze its own command bus timings internally. The on-die logic analyzer captures timing information about commands received from the host and stored in memory, allowing the device to self-diagnose timing issues without requiring external measurement equipment. This self-measurement capability accelerates debugging while maintaining measurement precision through dedicated timing analysis circuitry.
Data Source
AI summary
An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.