On-Die Memory Buffering for High-Speed Multi-Die Data Transfer
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Solution Overview
Problem
Increasing the number of semiconductor memory die in a system increases capacitive loading on signal lines, reducing the maximum data transmission rate.
Innovation Solution
Implementing a master semiconductor memory die that buffers data for slave memory dies, reducing capacitive loading by using on-die data buffering techniques, and eliminating the need for external data buffer integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of semiconductor memory die is increased to expand storage capacity, then storage capacity is improved, but capacitive loading on signal lines increases and maximum data transmission rate decreases
Solution Approach 1:
The patent introduces an intermediary data buffering mechanism within the memory system architecture. A data buffer is inserted between the memory controller and multiple memory die to mediate data transmission. This buffer absorbs the capacitive loading effects by providing local data storage capability, allowing the memory controller to transmit data at higher rates without being bottlenecked by the cumulative capacitance of multiple memory die. The buffer acts as a shock absorber that decouples the transmission speed from the loading effects.
Solution Approach 2:
The patent segments the data transmission path into multiple stages: the memory controller transmits data to a data buffer, which then selectively forwards data to individual memory die. This segmentation breaks the direct connection between the controller and multiple die, allowing independent optimization of each segment. The buffer segment handles the capacitive loading management, while the controller segment can operate at maximum speed.
2Quantity of substance
If the number of semiconductor memory die is increased to expand storage capacity, then storage capacity is improved, but engineering complexity increases due to signal line loading challenges
Solution Approach 1:
The data buffer is designed as a universal component that can serve multiple memory die simultaneously. Rather than requiring separate buffering or complex routing for each die, a single multi-functional buffer handles data distribution to multiple targets. This universal approach simplifies the engineering complexity by providing a standardized data distribution mechanism that scales with the number of memory die without proportionally increasing system complexity.
3Speed
If external data buffer integrated circuits are used to reduce capacitive loading, then data transmission rate is improved, but device complexity and routing requirements increase
Solution Approach 1:
The patent merges the data buffering function with the memory system architecture itself rather than using separate external buffer ICs. The buffer is integrated into the data path between the controller and memory die, combining multiple functions (data reception, buffering, and distribution) into a unified structure. This merging eliminates the need for additional external components and their associated routing, simplifying the overall circuit board design while maintaining high data transmission rates.
Data Source
AI summary
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.