On-Die Termination Layout for Multi-Die Memory Signal Integrity
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Solution Overview
Problem
In high-speed storage devices, signal integrity between non-volatile memory and a controller is a critical factor affecting overall performance, but existing technologies do not adequately address this issue due to lower operation frequencies compared to high-speed memories like DRAM or SRAM.
Innovation Solution
A non-volatile memory device with multiple memory dies, each equipped with an on-die-termination (ODT) circuit providing unique resistance values based on distance, position, and operation type to manage signal reflections effectively, enhancing signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed operation is implemented in non-volatile memory devices, then operation speed is improved, but signal integrity deteriorates due to signal reflections
Solution Approach 1:
The patent applies local quality by configuring different ODT resistance values for different memory dies based on their physical positions and distances from the controller. Specifically, memory dies closer to the controller are assigned different ODT values than those farther away, creating position-specific termination characteristics that locally optimize signal integrity for each die's location in the stack
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting ODT resistance values based on operational conditions. The system changes ODT parameters according to the target die's position, distance from controller, and operation type (read/write), thereby adapting the termination characteristics to match the specific signal path conditions and minimize reflections at different operating points
2Quantity of substance
If multiple memory dies are stacked vertically, then storage capacity is improved, but signal reflection increases due to varying distances from controller
Solution Approach 1:
The patent addresses signal reflection in multi-die stacks by assigning position-specific ODT resistance values to each die based on its vertical distance from the controller. Dies at different levels in the stack receive customized ODT configurations that account for their specific signal path characteristics, thereby locally compensating for reflection issues caused by the vertical stacking arrangement
Solution Approach 2:
The patent segments the termination strategy by die position, dividing the multi-die stack into distinct groups based on their distances from the controller. Each segment (group of dies at similar distances) is assigned appropriate ODT values, allowing differentiated treatment of signal paths to various dies rather than applying a uniform termination approach to the entire stack
Data Source
AI summary
Provided is a non-volatile memory device including an input/output (I/O) pin configured to transfer data to or receive data from a memory controller, and a plurality of memory dies connected to the I/O pin, the plurality of memory dies including a target die, a first non-target die, and a second non-target die, wherein the first non-target die includes a first on-die-termination (ODT) circuit connected to the I/O pin and provides a first ODT resistance value based on a first distance between the target die and the first non-target die, and wherein the second non-target die includes a second ODT circuit connected to the I/O pin and provides a second ODT resistance value based on a second distance between the target die and the second non-target die, the second ODT resistance value being different from the first ODT resistance value.