On-Die Termination Circuits for Multi-Bank Memory Signal Integrity
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Solution Overview
Problem
In packaged multi-bank memory devices, signal distortion and integrity issues arise during high-speed operations due to unmanaged on-die-termination (ODT) resistance, particularly when multiple memory devices are simultaneously driven by a host.
Innovation Solution
The implementation of an ODT setting circuit and ODT enable circuit that dynamically adjust ODT resistance based on control commands and signals from the host, ensuring that only memory devices receiving an ODT request connect ODT resistance to signal pads, while others connect it based on an ODT flag signal, thereby minimizing signal reflection and maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory devices are simultaneously driven by a host to improve operating speed, then productivity increases, but signal distortion worsens due to unmanaged ODT resistance
Solution Approach 1:
The ODT resistance is made dynamically adjustable through control circuits that receive commands from the host and automatically set appropriate resistance values. The ODT setting circuit changes resistance values based on operating conditions, allowing the system to maintain signal integrity while operating multiple memory devices at high speeds.
Solution Approach 2:
The patent changes the electrical parameter (ODT resistance value) to resolve the contradiction. By adjusting the termination resistance parameter dynamically, the system can match impedance requirements for high-speed operation while preventing signal distortion that would occur with fixed resistance values.
2Reliability
If ODT resistance is connected in all memory devices to minimize signal reflection, then signal integrity improves, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent merges the ODT control functionality into a unified control structure where a control command from the host simultaneously manages ODT resistance across multiple memory devices. The ODT setting circuit and ODT enable circuit are integrated to work together, reducing overall system complexity while maintaining signal integrity.
Solution Approach 2:
The memory devices perform self-configuration of ODT resistance based on commands received from the host. The ODT setting circuit automatically adjusts resistance values without requiring external manual configuration, and the ODT enable circuit autonomously activates ODT based on control signals, reducing the burden on the host controller.
3Reliability
If ODT resistance value is set to match host request to minimize distortion, then signal integrity improves, but manufacturing precision requirements increase for resistor circuits
Solution Approach 1:
The patent uses programmable resistor circuits where resistance values can be changed through control signals rather than being fixed during manufacturing. This allows the system to achieve precise termination resistance values through electrical control rather than requiring extremely tight manufacturing tolerances on physical resistors.
Solution Approach 2:
The resistor circuit is designed to be dynamically adjustable rather than fixed, allowing post-manufacturing configuration of precise resistance values. This dynamic capability compensates for manufacturing variations and enables precise impedance matching without requiring ultra-precise resistor fabrication.
Data Source
AI summary
A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.