On-Die Termination Timing Control for Memory Signal Integrity
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Solution Overview
Problem
Existing signal transmitting and receiving apparatuses and memory devices face performance degradation due to the simultaneous enabling and disabling of on-die termination circuits, which causes preamble and postamble time issues during signal transmission and reception.
Innovation Solution
The apparatus includes independent control over the enable and disable timing of first and second on-die termination circuits connected to different pins, allowing the second circuit to be enabled only after the first, thereby preventing performance degradation by allowing signal transmission or reception before the second circuit is enabled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If on-die termination circuits are simultaneously enabled and disabled, then signal transmission is simplified, but performance degradation occurs due to preamble and postamble time issues
Solution Approach 1:
The patent divides the on-die termination control into separate circuits for different signal types (e.g., data signals and clock signals). Each termination circuit can be independently enabled or disabled based on its specific timing requirements, allowing differential control that prevents performance degradation while maintaining overall system manageability.
2Productivity
If the second on-die termination circuit is enabled before the first, then both circuits can operate simultaneously, but performance degradation occurs due to timing conflicts
Solution Approach 1:
The patent implements a control mechanism where the first on-die termination circuit is enabled before the second circuit. This preliminary enabling sequence ensures that the first circuit is ready to handle signals without interference from the second circuit, preventing timing conflicts and performance degradation while maintaining efficient signal transmission.
Data Source
AI summary
A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.