On-Die Voltage Modulation for Weak Bit Detection
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Solution Overview
Problem
Variations in electrical characteristics among data storage cells in semiconductor memory circuits due to manufacturing and aging effects lead to inconsistent performance, requiring external testing that is time-consuming and costly.
Innovation Solution
An integrated circuit with on-chip circuitry capable of performing a disturb test by changing the power supply voltage level and comparing read results to test data, allowing for identification of problematic cells without external devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test devices are used to detect data storage cells with varying electrical characteristics, then measurement precision is improved, but device complexity and test time increase
Solution Approach 1:
The patent merges the testing functionality into the memory device itself by incorporating test circuits and control logic within the memory chip. This allows the device to self-test without requiring external test equipment, thereby reducing device complexity while maintaining measurement precision for detecting storage cells with varying electrical characteristics.
Solution Approach 2:
The memory device performs its own testing through integrated test circuits that can detect and characterize the electrical properties of individual storage cells. This self-service capability eliminates the need for external test devices, reducing system complexity while enabling precise measurement of cell characteristics through on-chip analog signal generation and comparison.
2Measurement precision
If external test devices are employed for storage cell detection, then measurement precision is improved, but loss of time increases
Solution Approach 1:
By integrating test functionality directly into the memory device architecture, the patent enables parallel testing of multiple storage cells simultaneously using on-chip test circuits. This eliminates the sequential testing process required by external devices, significantly reducing test time while maintaining detection accuracy through integrated analog signal generation and comparison capabilities.
3Reliability
If variations in manufacturing and aging effects are present, then reliability is reduced, but manufacturing precision cannot be improved
Solution Approach 1:
The patent implements local quality adjustment by providing individual storage cells with adjustable test points and localized test circuits that can characterize each cell's electrical characteristics. This allows for cell-by-cell identification and classification of cells affected by manufacturing variations and aging, enabling reliability improvement through targeted replacement or compensation without requiring improved manufacturing precision.
Solution Approach 2:
The integrated test circuits provide feedback signals that characterize the electrical properties of each storage cell and feed this information to control logic. This feedback mechanism enables the system to identify and compensate for cells with degraded performance due to manufacturing variations or aging effects, maintaining reliability without requiring changes to the manufacturing process itself.
Data Source
AI summary
Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.