On-Memory CRC Tracking for Targeted Write Transaction Retries
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Solution Overview
Problem
As memory subsystem data rates and pin counts increase, the ability to meet overall bit error rate (BER) targets becomes more difficult, and existing CRC methods for write transactions in memory systems are inefficient in identifying specific error transactions, leading to unnecessary retries of all transactions within a period.
Innovation Solution
Implementing on-memory CRC circuitry in memory devices to compute and compare CRC for write transactions, record pass/fail status in an error status register, and trigger an alert signal, allowing the memory controller to identify and retry only the specific transaction with an error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC is applied to all write transactions to improve reliability, then bit error rate target is met, but the complexity of tracking and managing error transactions increases
Solution Approach 1:
The patent segments the tracking of error transactions by assigning unique identifiers (such as transaction IDs or sequence numbers) to each write transaction. This allows the system to divide the complex task of tracking all CRC errors into manageable units, where each error can be individually identified and tracked without overwhelming complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller receives acknowledgment signals from the memory device about CRC check results. This feedback loop allows the controller to learn which specific transactions had errors and adjust its retry strategy accordingly, reducing the complexity of manual tracking while maintaining high reliability.
2Reliability
If all transactions within a period are retried to ensure error correction, then data integrity is improved, but the time loss and latency increase
Solution Approach 1:
The patent extracts only the problematic transactions that failed CRC checks from the set of all recent transactions. Instead of retrying all transactions within a period, the system identifies and retries only the specific transactions with CRC errors, thereby reducing unnecessary time consumption while maintaining data integrity for affected data.
Solution Approach 2:
The patent applies partial action by retrying only the necessary transactions (those with CRC errors) rather than performing excessive actions (retrying all transactions). This selective approach minimizes time loss while ensuring that data integrity is restored for the specific corrupted data without wasting time on already successful transactions.
3Reliability
If CRC checking is performed on all write transactions, then error detection capability is improved, but the productivity of the memory subsystem decreases
Solution Approach 1:
The patent performs preliminary CRC calculation and checking during the write transaction itself, before the data is fully committed to memory. This preliminary action allows errors to be detected and corrected in-place without requiring subsequent retransmissions of entire data blocks, thereby maintaining high productivity while ensuring error detection.
Solution Approach 2:
The patent implements self-service by having the memory device perform CRC checking on its own during write operations, without requiring continuous intervention or monitoring from the memory controller. This autonomous error detection capability maintains reliability while minimizing the overhead on the overall memory subsystem productivity.
Data Source
AI summary
A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass/fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.