On-Package Capacitors on Interposal Layer for Substrate Size Reduction
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Solution Overview
Problem
The existing IC packages require a larger substrate to accommodate decoupling capacitors, leading to increased packaging costs and manufacturing risks due to the need for a bigger packaging substrate with a bigger die.
Innovation Solution
The implementation of on-package decoupling capacitors (OPD) by placing a thinner substrate layer with capacitors on top of the IC and connecting them to the build-up substrate with wires, allowing for a smaller packaging substrate size without compromising the number of capacitors that can be accommodated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If decoupling capacitors are placed on the substrate layer surrounding the die, then the capacitors can be accommodated in the IC package, but the substrate size must be increased to provide ample space between the die and capacitors
Solution Approach 1:
The patent transitions from a two-dimensional layout where capacitors are placed on the substrate plane to a three-dimensional configuration by stacking capacitors vertically on an interposal layer between the die and the substrate. This vertical stacking enables multiple capacitors to be accommodated without increasing the substrate area, directly resolving the contradiction between capacitor quantity and substrate size.
Solution Approach 2:
The interposal layer acts as a nested structure between the die and the substrate, creating an intermediate platform for capacitor placement. This nested configuration allows capacitors to be embedded within the vertical space of the package rather than occupying horizontal substrate area, enabling high capacitor density without substrate expansion.
2Quantity of substance
If a bigger substrate is used to accommodate more capacitors, then all necessary capacitors can be included in the package, but packaging cost and manufacturing risks increase
Solution Approach 1:
By utilizing the vertical dimension through interposal layer stacking, the patent achieves high capacitor integration without requiring larger substrates. This maintains manageable substrate sizes, thereby controlling manufacturing complexity and reducing packaging risks associated with handling and processing large substrates.
Solution Approach 2:
The interposal layer serves as an intermediary structure that decouples the relationship between substrate size and capacitor capacity. It provides a dedicated platform for vertical capacitor stacking, allowing the substrate to remain compact while still accommodating numerous capacitors through the intermediate layer's vertical space utilization.
Data Source
AI summary
An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.