On-Package I/O Architecture for Low Power Interconnects
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Solution Overview
Problem
Conventional high-bandwidth interconnections between chips require significant power and chip area, making them undesirable for applications needing reduced power consumption and smaller chip size.
Innovation Solution
The development of an On-Package I/O (OPIO) interface that uses single-ended, high-speed CMOS interfaces with impedance-matched transmitters, forwarded clock signals, and reduced electrostatic discharge protection to achieve high bandwidth with low power, area, and latency, enabling efficient interconnection of chips in a Multi-Chip Package (MCP).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional I/O interfaces are used for high-bandwidth interconnections between chips, then bandwidth is achieved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent changes the electrical parameters of the I/O interface by using single-ended signaling instead of differential signaling, reducing the voltage swing and current requirements. This parameter change enables high bandwidth operation while significantly reducing power consumption compared to conventional interfaces
Solution Approach 2:
The patent extracts and eliminates unnecessary components from the conventional I/O interface architecture, such as removing the need for complex termination networks and equalization circuits. This extraction simplifies the interface while maintaining high bandwidth capability with reduced power consumption
2Productivity
If conventional I/O interfaces are used for high-bandwidth interconnections between chips, then bandwidth is achieved, but chip area increases significantly
Solution Approach 1:
The patent removes unnecessary components and circuitry from the conventional I/O interface, such as complex termination networks, equalization circuits, and shielding structures. This extraction reduces the chip area required for the interface while maintaining high bandwidth capability
Solution Approach 2:
By changing the signaling parameters to single-ended operation with reduced voltage swings, the patent reduces the size of required components and interconnect structures, thereby reducing the overall chip area needed for high-bandwidth interfaces
3Speed
If reduced electrostatic discharge protection is used in OPIO interface, then pad capacitance decreases and data rate increases, but protection against ESD reduces
Solution Approach 1:
The patent changes the ESD protection parameter by reducing the protection voltage level and simplifying the protection circuitry. This parameter change reduces pad capacitance and enables higher data rates, while the protection level is adjusted to be adequate for the specific application environment
Data Source
AI summary
An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.