On-Pitch Drain Select Gate Layout for 3D Memory Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving optimal performance due to the lack of efficient select gate electrode designs that match the periodicity of memory stack structures, leading to suboptimal storage density and operational efficiency.
Innovation Solution
A three-dimensional memory device is designed with on-pitch select gate electrodes that have the same periodicity as the memory stack structures, featuring an alternating stack of insulating and conductive layers, drain select level assemblies, and a perforated dielectric strip isolation, which allows for precise alignment and enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional select gate electrode designs are used, then manufacturing is simpler, but storage density and operational efficiency deteriorate due to misalignment with memory stack periodicity
Solution Approach 1:
The select gate electrode is segmented into multiple cylindrical portions arranged in rows, with each cylinder corresponding to a specific memory stack. This segmentation enables precise alignment with the periodic memory stack structure while maintaining manufacturability through modular formation processes.
Solution Approach 2:
The electrode structure transitions from a conventional planar configuration to a three-dimensional array of cylindrical portions. This dimensional change allows the electrode to match the vertical and horizontal periodicity of the memory stacks, achieving superior alignment precision without proportionally increasing manufacturing complexity.
2Productivity
If on-pitch select gate electrodes with same periodicity as memory stacks are implemented, then storage density and operational efficiency improve, but manufacturing precision requirements increase
Solution Approach 1:
Dielectric spacers are formed around the memory stacks before the select gate electrode portions are created. These pre-formed spacers serve as alignment templates, enabling the electrode cylinders to be precisely positioned at the correct pitch relative to the memory stacks without requiring ultra-precise direct alignment processes.
Solution Approach 2:
The dielectric spacers act as intermediary structures that mediate between the memory stacks and the select gate electrodes. By forming electrodes around these spacers rather than directly around stacks, the manufacturing process achieves the required precision through a buffered, multi-step formation process.
3Reliability
If drain select level assemblies are added to match memory stack periodicity, then electrical connectivity improves, but device complexity increases
Solution Approach 1:
The select gate electrode structure serves multiple functions simultaneously: it provides electrical connectivity to drain regions, acts as a control gate for select transistors, and maintains the periodicity required for high-density stacking. This multi-functionality improves reliability without proportionally increasing complexity.
Solution Approach 2:
The drain select level assemblies are merged with the alternating stack structure, where drain regions are integrated at specific levels within the stack. This combining of functions into a unified periodic structure achieves improved electrical connectivity while minimizing the increase in overall device complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.