On-Pitch Via Layout for Uniform Current in 3D Memory Arrays
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Solution Overview
Problem
Memory devices face challenges in maintaining uniform electrical characteristics due to nonuniform processing conditions in the socket region, leading to reduced yield and reliability issues caused by proximity effects on on-pitch vias.
Innovation Solution
Modifying the lengths of on-pitch vias based on their distance from the memory array to enhance their surface area and robustness against chemical-mechanical polishing, thereby reducing variations in electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If on-pitch vias are used to connect access lines to CMOS circuitry, then device density and integration are improved, but nonuniform processing conditions in the socket region cause variations in electrical characteristics
Solution Approach 1:
The patent applies local quality by differentiating the treatment of near on-pitch vias versus far on-pitch vias based on their location relative to the memory array. Near on-pitch vias, which are more susceptible to proximity effects and nonuniform processing conditions, receive enhanced protection through additional dielectric material deposition. This localized modification ensures that vias in critical regions maintain uniform electrical characteristics while preserving the high-density benefits of on-pitch via architecture throughout the device.
2Ease of manufacture
If standard dielectric removal is performed, then manufacturing simplicity is maintained, but chemical-mechanical polishing causes nonuniform surface conditions affecting via robustness
Solution Approach 1:
The patent implements beforehand cushioning by depositing an additional layer of dielectric material specifically over near on-pitch vias before the chemical-mechanical polishing step. This pre-applied protective layer acts as a cushion that compensates for the nonuniform material removal during polishing, ensuring that the via surfaces remain robust and uniform. The approach maintains manufacturing simplicity by using standard deposition and polishing processes while adding only one targeted dielectric layer to protect critical vias.
3Manufacturing precision
If uniform via dimensions are used throughout the device, then manufacturing consistency is improved, but proximity effects cause nonuniform current distribution in the memory array
Solution Approach 1:
The patent resolves this contradiction by applying local quality through selective modification of near on-pitch vias. While far on-pitch vias maintain standard dimensions for manufacturing consistency, near on-pitch vias receive additional dielectric material that compensates for proximity effects. This localized enhancement ensures that despite uniform manufacturing processes, the electrical characteristics and current distribution across the memory array become more uniform, as the protected vias in critical regions maintain their intended electrical properties.
Data Source
AI summary
Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.