On-Product Clock Generation for Multi-Domain Test Sequences
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Solution Overview
Problem
Current methods for testing electronic circuits with multiple clock domains are inefficient due to the need for high-frequency clocks, which are costly and difficult to generate, and result in race conditions and increased test time when trying to pulse multiple domains simultaneously.
Innovation Solution
A method and system for generating on-product clock pulses for multiple clock domains using a base clock signal and programming instructions, allowing for independent delay settings and simultaneous pulsing of clock domains with a delay mechanism to avoid race conditions, reducing the need for additional scan-in pins and improving test compression efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple clock domains are pulsed simultaneously to reduce test time, then productivity improves, but race conditions occur and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by introducing a delay mechanism that pre-calculates and implements timing offsets between clock domain pulses. The delay circuitry is configured in advance to ensure that clock domains are pulsed in a controlled sequence rather than simultaneously, eliminating race conditions while maintaining high test throughput. This allows multiple domains to be tested in parallel without compromising reliability.
2Ease of operation
If dedicated scan-in pins are added for OPCG programming to avoid bandwidth competition, then ease of operation improves, but device complexity increases
Solution Approach 1:
The patent applies universality by designing scan-in pins to serve multiple functions: they can load both normal scan chain test data and OPCG programming bits through a single pin interface. The decompression logic is enhanced to handle both types of data streams simultaneously, eliminating the need for separate dedicated pins for OPCG programming while maintaining programming flexibility and avoiding additional hardware complexity.
3Device complexity
If OPCG programming bits are loaded via decompression logic to save pins, then device complexity reduces, but loss of information increases due to bandwidth competition with ATPG care bits
Solution Approach 1:
The patent applies segmentation by separating the loading of OPCG programming bits from the loading of normal scan chain test data. The system uses a dual-mode scan chain mechanism where programming bits are loaded in a first mode through decompression logic, and test data is loaded in a second mode. This temporal and functional segmentation allows both types of data to be loaded without competing for the same bandwidth resources, preventing information loss while maintaining pin efficiency.
4Measurement precision
If high-frequency clocks are generated using PLL circuits to enable at-speed testing, then measurement precision improves, but device complexity and cost increase
Solution Approach 1:
The patent applies self-service by implementing on-product clock generation where the Device Under Test (DUT) generates its own high-frequency test clocks using integrated PLL circuits and clock dividers. The DUT's clock generation infrastructure is utilized to produce at-speed test clocks without requiring external ATE equipment to provide these high-frequency signals. This self-service approach eliminates the need for complex external clock generation hardware while maintaining measurement precision for at-speed testing.
Data Source
AI summary
A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal and a second delay for the second clock signal are determined from the programming instruction. A test sequence is provided to test a first clock domain and a second clock domain. The test sequence comprises the first clock signal delayed by the first delay and the second clock signal delayed by the second delay. The first clock drives the first clock domain and the second clock derives the second clock domain.