On-Substrate EEPROM Structure for Glass Integration
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Solution Overview
Problem
Current EEPROM structures require mounting on a printed circuit board due to external formation, leading to increased packaging costs, size, and reduced data access speed, especially when integrated with glass substrates.
Innovation Solution
A single-poly silicon EEPROM structure is formed directly on a substrate, such as a glass substrate, using spaced semiconductors with floating gates and ion-doped regions, allowing for electrical connection between floating gates to control thermal electron tunneling for data writing and erasing, eliminating the need for a flexible printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the EEPROM is formed externally on a separate substrate, then the memory structure can be independently manufactured, but the packaging cost increases and the data access speed decreases
Solution Approach 1:
The patent merges the EEPROM structure with the glass substrate by forming the EEPROM directly on the glass substrate using the same thin-film deposition processes. This integration eliminates the need for separate manufacturing and mounting steps, thereby increasing data access speed while maintaining manufacturing ease through standardized thin-film fabrication techniques.
2Ease of operation
If the EEPROM is mounted on a printed circuit board via flexible printed circuit board, then the EEPROM can be electrically connected to the glass substrate, but the package size becomes bigger and thicker
Solution Approach 1:
The EEPROM is merged with the glass substrate by forming it directly on the substrate surface using thin-film deposition. This integration eliminates the need for external mounting components such as flexible printed circuit boards, thereby reducing package size and thickness while maintaining electrical connection capability through direct integration.
3Area of stationary object
If neighboring MOS elements are formed close together to reduce area, then the device area decreases, but latch up occurs between the MOS elements
Solution Approach 1:
The patent introduces an n-type diffusion layer as an intermediary between adjacent MOS elements. This intermediate layer acts as a protective barrier that prevents latch-up by providing a low-resistance path for minority carriers, thereby allowing MOS elements to be placed closer together while maintaining reliability.
Solution Approach 2:
The patent applies local quality by introducing n-type diffusion regions specifically in the p-type substrate areas between MOS elements, while maintaining the original doping in the MOS regions. This localized modification prevents latch-up only where needed, allowing optimal spacing between MOS elements while maintaining small device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces packaging costs, enhances data access speed, and decreases image processing reaction time by integrating the EEPROM directly onto the glass substrate, eliminating the need for a flexible printed circuit board.
Implementation Method 1
two lateral ends of the first semiconductor under the first floating gate are ion-doped to form respective N+-type ion-doped regions
Implementation Method 2
different control voltages Vg are utilized to determine the 'tunneling' of thermal electrons to the floating gate
Data Source
AI summary
An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.