On-Board Memory Processing Logic for Parallel System Bottlenecks
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Solution Overview
Problem
The increasing number of processing cores and threads in computer systems leads to communication bottlenecks due to high latencies and software overheads, as most systems rely on message passing rather than shared memory, making it difficult to effectively apply parallelism to tasks like weather prediction.
Innovation Solution
A memory device with integrated processing system that enables efficient access by allowing operations to be performed in an indivisible manner, using coherency circuitry and Boolean logic operations to reduce coherency issues and improve communication between processors, allowing for natural coherence and reduced software overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing cores and threads is increased to enhance parallelism, then system performance is improved, but communication overhead and latency increase disproportionately
Solution Approach 1:
The patent merges message passing and shared memory access into a unified memory interface. The memory device integrates processing logic that can directly receive and execute instructions from multiple processors simultaneously, combining the benefits of both message passing (direct processor-to-memory communication) and shared memory (simultaneous access) into a single coherent system that eliminates the need for separate communication paths.
Solution Approach 2:
The memory device is designed with universal functionality to serve multiple processors concurrently. It can operate in different modes (read, write, execute, compare) and handle various data types (bytes, words, doublewords, quadrupledwords) through a single interface, allowing any processor to access any memory location without dedicated communication paths.
2Device complexity
If message passing is used to simplify system architecture, then architectural complexity is reduced, but software overhead and processing efficiency deteriorate
Solution Approach 1:
The memory device provides self-service by integrating processing logic directly within the memory array. The memory can autonomously execute instructions, perform comparisons, and manage data operations without requiring external processor intervention for each operation. This eliminates the software overhead associated with message passing while maintaining architectural simplicity.
3Reliability
If processors are dedicated to managing message traffic, then communication coordination is improved, but actual useful work decreases
Solution Approach 1:
The patent extracts the communication management function from the processors and relocates it to the memory device. The memory device's integrated processing logic handles all communication coordination, address decoding, and data management tasks, freeing processors to focus exclusively on executing application logic and performing useful computational work.
Data Source
AI summary
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.