On-chip Jitter Evaluation for SerDes Receivers
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Solution Overview
Problem
In digital communications, timing jitter caused by channel non-idealities and discrepancies in clock signals between transmitters and receivers can lead to unreliable link performance, making it difficult for receiving devices to accurately determine symbol transitions, especially when combined with additive noise and intersymbol interference.
Innovation Solution
An integrated circuit with a timing recovery circuit that determines a phase offset signal from estimated timing errors and an on-chip memory to capture this signal, allowing a processor to derive jitter measurements such as probability distribution, mean-square value, and frequency transform, which can indicate link quality and trigger corrective actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing jitter is not measured and monitored, then the system operates without additional measurement complexity, but link reliability deteriorates due to undetected timing errors
Solution Approach 1:
The receiver performs self-diagnosis by monitoring its own timing recovery performance. The timing recovery circuit's phase offset signal is captured and analyzed by an on-chip processor to detect jitter conditions, allowing the system to self-identify link quality issues without external measurement equipment.
Solution Approach 2:
An on-chip memory buffer serves as an intermediary between the timing recovery circuit and the processor. It captures and stores phase offset signals, enabling the processor to analyze jitter characteristics without directly interfacing with the high-speed timing circuitry, thus simplifying the measurement system architecture.
2Measurement precision
If jitter measurements are implemented, then link quality can be detected and corrective actions initiated, but the device complexity increases due to additional circuits and processing
Solution Approach 1:
The jitter measurement function is extracted as a separate analytical process from the main data reception function. The processor derives jitter measurements specifically from the captured phase offset signal, separating the measurement task from the primary communication function to minimize interference and simplify implementation.
Solution Approach 2:
The phase offset signal is captured in memory before jitter analysis is performed. This preliminary capture allows the system to accumulate sufficient data for accurate statistical analysis (mean-square, RMS, probability distribution) without requiring complex real-time processing during high-speed operation.
3Loss of information
If phase offset signals are captured for jitter analysis, then timing jitter can be characterized, but memory resources are consumed
Solution Approach 1:
The system captures phase offset signals at a sufficient rate to accurately characterize jitter, using enough memory capacity to store the data needed for reliable statistical analysis. This partial action approach captures only the essential timing error information required for jitter measurement without storing excessive data that would waste memory resources.
Data Source
AI summary
An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.