On-Chip RC Oscillator Chopping to Reduce RTN Timing Drift

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Solution Overview

Problem

Low-drift fully integrated low power oscillators in system-on-chip (SOC) are susceptible to Random Telegraph Noise (RTN), which jeopardizes the timing precision required for sleep modes in battery-powered RF-SOC applications.

Innovation Solution

The system employs a low-drift on-chip oscillator with chopped current sources, where transistors M1 and M2 are alternately connected to the ring oscillator and control resistor for 50% of the time, reducing the impact of RTN noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a fully integrated low-drift RC oscillator is used in deep submicron CMOS technologies, then power consumption is minimized and integration is achieved, but sensitivity to Random Telegraph Noise (RTN) increases, jeopardizing timing precision

Engineering Contradiction:
Improvepower consumptionVSAvoidtiming precision
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The current source is divided into two parallel branches (first current source and second current source), each contributing to the total current but independently susceptible to RTN. This segmentation allows the noise from each branch to partially cancel out when combined, reducing overall RTN sensitivity while maintaining the same total current and power consumption level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Two parallel current sources are merged to form the total current Id for the ring oscillator. The merging of these independent current paths creates a combined current that benefits from noise cancellation, where RTN fluctuations in one branch are offset by fluctuations in the other branch, thereby improving timing precision without increasing power consumption.

Inventive Principle:
Principle #5Merging (Combining)

2Duration of action of stationary object

If conventional current sources are used in the oscillator, then the oscillator operates continuously with low power, but RTN noise reduces the precision of predefined time in sleep modes

Engineering Contradiction:
Improvecontinuous operationVSAvoidtiming precision in sleep modes
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The current source is segmented into two parallel independent current sources, each operating continuously but with independent RTN characteristics. This segmentation enables the oscillator to maintain continuous low-power operation while the combined effect of both current sources reduces RTN impact on timing precision during sleep modes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The oscillator includes a feedback mechanism where the output of the ring oscillator feeds back to the input, creating a stable oscillating signal. This feedback loop, combined with the parallel current sources, ensures continuous stable operation and allows the system to maintain precise timing even in sleep modes by compensating for RTN fluctuations through the inherent stability of the oscillating signal.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12341517B2System with a low-drift on-chip oscillator with lowered sensitivity to random telegraph noise
Publication Date: 2025.06.24 EM MICROELECTRONIC-MARIN
  • US12341517B2 patent drawing
  • US12341517B2 patent drawing
  • US12341517B2 patent drawing

AI summary

A system with a low-drift on-chip (LD-RC) oscillator with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator. A control resistor (R) is connected through an intermediary arrangement to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd). The gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source.