On-Demand PHY Error Correction for Low-Latency Packet Links
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Solution Overview
Problem
In packet network communications, physical-layer error correction introduces latency due to the need for entire FEC blocks to be received before correction can begin, which may outweigh its benefits in networks with low bit-error rates where errors are rare.
Innovation Solution
Implementing a selective physical-layer error correction mechanism where the error correction circuit operates only when errors are detected, buffering data blocks and using flow control to manage transmission, allowing the PHY interface to pass data to the data link layer until errors are corrected, thereby minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous physical-layer error correction is implemented using FEC blocks, then error correction reliability is improved, but transmission latency increases due to waiting for entire FEC blocks
Solution Approach 1:
The error correction circuit is dynamically activated only when errors are detected by the data link layer, rather than operating continuously. This dynamic switching allows the system to maintain low latency during error-free transmission while providing error correction capability when needed, resolving the contradiction between reliability and latency
Solution Approach 2:
The system changes the operational state of the error correction circuit based on error detection results. When the data link layer detects errors, the parameter of error correction circuit activation changes from inactive to active, enabling correction without requiring continuous operation and thus reducing average latency while maintaining reliability
2Productivity
If on-demand error correction is implemented, then transmission efficiency is improved by reducing latency, but error correction capability may be insufficient without proper buffering
Solution Approach 1:
Data blocks are buffered in advance at the PHY interface before error detection occurs. This preliminary buffering ensures that when errors are detected by the data link layer, the original data blocks are already available for immediate error correction, maintaining both transmission efficiency and error correction capability
Solution Approach 2:
The buffer acts as an intermediary between the data link layer and the error correction circuit. It stores data blocks temporarily, allowing the data link layer to detect errors and request correction without disrupting the overall transmission flow, thus maintaining productivity while ensuring reliability
Data Source
AI summary
Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.