On-Die Current-to-Frequency Circuit for Non-Destructive Mismatch Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for analyzing transistor mismatches in integrated circuits are time-consuming and destructive, limiting the ability to collect comprehensive current measurement data across dies and reducing yield, as they require physical modification and destructive testing.
Innovation Solution
A current measurement circuit that uses a current-to-clock conversion technique, allowing for non-destructive measurement of currents across transistors at various spatial locations on an integrated circuit die, utilizing a small current monitor distributed across the die to generate output counts proportional to current magnitudes, enabling high spatial granularity without altering the silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical failure analysis operations are performed to delayer metal layers and build probe pads for current measurements, then current measurement capability is achieved, but the process becomes time-consuming and destructive to the circuitry
Solution Approach 1:
The patent incorporates dedicated test matched devices and probe pad structures into the circuit design before fabrication. These preliminary structures are built during the standard manufacturing process, eliminating the need for time-consuming post-fabrication delayering and probe pad construction. The test matched devices include pre-configured transistor pairs with accessible terminals that can be measured directly after packaging.
Solution Approach 2:
The patent creates physical copies of the production circuitry in the form of test matched devices fabricated in the scribe line areas. These test devices replicate the electrical characteristics of the production transistors but are designed with accessible probe pads. By measuring these copies instead of the production devices themselves, the patent enables non-destructive current measurements without affecting yield.
2Measurement precision
If physical failure analysis operations are performed to delayer and build probe pads, then current measurements can be obtained, but the die becomes unusable and must be discarded
Solution Approach 1:
The patent separates the testing function from the production function by fabricating test matched devices in the scribe line areas, which are the empty spaces between individual dies on the wafer. This segmentation allows test measurements to be performed on dedicated test structures without affecting the production dies. The probe pads for these test devices are built in the scribe line, keeping the production die areas intact and usable.
Solution Approach 2:
The patent creates physical copies of the production circuitry in the form of test matched devices fabricated in the scribe line areas. These test devices replicate the electrical characteristics of the production transistors but are designed with accessible probe pads. By measuring these copies instead of the production devices themselves, the patent enables non-destructive current measurements without affecting yield.
3Ease of manufacture
If test matched devices are fabricated in empty areas or scribe line, then fabrication complexity is reduced, but spatial granularity for detecting intra-die variations is insufficient
Solution Approach 1:
The patent extends the testing capability from the horizontal plane to the vertical dimension by utilizing the scribe line area, which is the empty space surrounding each die on the wafer. By fabricating test matched devices in this third dimension (the peripheral area), the patent achieves both high spatial granularity for intra-die variation detection and ease of manufacture, as these test devices can be accessed through probe pads built in the scribe line without affecting the production die areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for current measurements, maintains yield by avoiding physical damage, and allows for efficient identification of transistor mismatches and root causes across the die.
Implementation Method 1
a first integration capacitor having a first terminal that is coupled to a first terminal of a first switch and having a second terminal that is coupled to both a first input terminal of a first operational amplifier
Implementation Method 2
during operation, the clocking circuit generates a two-phase clock having a frequency that is proportional to the input current
Data Source
AI summary
In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.