On-Die Data Processing Circuit in 3D NAND Memory

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Solution Overview

Problem

Conventional 3D memory devices face inefficiencies due to large peripheral circuits occupying chip space, limiting array efficiency and requiring external data processing, which slows down I/O speed and increases costs, and the thermal budget restricts high-speed data processing.

Innovation Solution

Incorporating an on-die data processing circuit within the 3D memory device, integrated with peripheral circuits, to perform operations directly on the memory array, reducing the need for external processing and enhancing I/O throughput by enabling high-speed data processing on-chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If peripheral circuits are integrated in 3D memory devices, then device functionality is improved, but chip space is consumed and array efficiency is limited

Engineering Contradiction:

Improvedevice functionalityVSAvoidchip space

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar 2D integration to 3D vertical integration by stacking memory cells and circuits in multiple layers. This allows peripheral circuits to be integrated without consuming lateral chip space, as components are arranged in the vertical dimension rather than occupying horizontal area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If external data processing is used, then data processing capability is provided, but I/O speed is reduced and costs increase

Engineering Contradiction:

Improvedata processing capabilityVSAvoidI/O speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent combines data processing circuits with the memory array on the same chip, merging storage and computation functions into a single integrated device. This eliminates the need for separate external data processing units and reduces data transfer distances, thereby improving I/O speed while providing on-chip data processing capability.

Inventive Principle:

Principle #5Merging (Combining)

3Quantity of substance

If planar memory cells are scaled to smaller sizes, then memory density is improved, but process technology becomes challenging and costly

Engineering Contradiction:

Improvememory densityVSAvoidprocess technology

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent adopts 3D vertical stacking architecture instead of continuing to scale planar 2D memory cells. By building memory cells vertically in multiple layers with through-silicon vias and stacked transistor structures, the design achieves high memory density without requiring further reduction of lateral feature sizes, thus avoiding the manufacturing challenges and costs associated with extreme planar scaling.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11461266B2Computation-in-memory in three-dimensional memory device

Publication Date: 2022.10.04 YANGTZE MEMORY TECH CO LTD

AI summary

Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a 3D NAND memory array and an on-die data processing circuit coupled to the 3D NAND memory array on a same chip. The on-die data processing circuit is configured to receive, from an input/output (I/O) interface, control instructions for performing operations on data stored in the 3D NAND memory array. The on-die data processing circuit is also configured to retrieve the data from the 3D NAND memory array based on the control instructions and perform the operations on the retrieved data. Moreover, the on-die data processing circuit is configured to return a result of the operations to the I/O interface.