On-Die Decoupling Capacitor for IR Drop Reduction
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Solution Overview
Problem
The increasing complexity and operational speeds of integrated circuits lead to high power consumption and reduced device noise margins due to IR drops in microelectronic systems, which are exacerbated by the distance of decoupling capacitors from the IC die, making them ineffective in mitigating power supply noise.
Innovation Solution
A microelectronic package with a discrete decoupling capacitor mounted directly on the chip or within a redistribution layer in close proximity to the IC die, utilizing surface mounting technology to reduce IR drops and improve power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are mounted on the packaging substrate or within the substrate, then power integrity is improved, but the distance to the IC die remains too large to effectively reduce on-chip IR drop
Solution Approach 1:
The patent transitions from mounting capacitors on the packaging substrate (2D plane) to mounting them directly on the IC die surface (3D integration), reducing the distance to the power distribution network by utilizing the vertical dimension and direct die attachment
Solution Approach 2:
The discrete passive element is placed within the package structure in a nested configuration, specifically mounted on the IC die itself or on an intermediate substrate layer that is in direct contact with the die, creating a hierarchical nesting that minimizes distance
2Use of energy by moving object
If the nominal supply voltage is reduced to manage power consumption, then power consumption decreases, but device noise margins are reduced making components more vulnerable to power supply noise
Solution Approach 1:
The patent changes the physical parameters of the power distribution system by introducing low-inductance decoupling capacitors in close proximity to the IC die, which compensates for the reduced noise margins caused by lower supply voltages through improved transient response
3Reliability
If decoupling capacitors are placed closer to the IC die to reduce transient response time, then power integrity improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the power integrity solution into discrete passive elements that can be independently selected and positioned, allowing optimization of transient response without requiring complete redesign of the entire package structure
Solution Approach 2:
The patent uses commercially available discrete passive elements with standard mounting technologies rather than custom-integrated solutions, reducing manufacturing complexity while achieving the required performance
Data Source
AI summary
A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.