On-Die ECC Check Bits Reduce Memory Power and Bandwidth
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Solution Overview
Problem
Traditional memory systems face challenges in scaling error checking and correction (ECC) without increasing the overhead, particularly in terms of bandwidth and power consumption, as the number of errors increases with smaller feature geometries, and existing solutions require additional pins and power to accommodate more ECC bits.
Innovation Solution
Implementing on-die ECC within memory devices, where the memory device generates and stores check bits for data, allowing for internal error correction and additional system bits to be exchanged with the memory controller, reducing the need for additional pins and power by using a logarithmic relationship between ECC bits and data bits, and enabling more robust ECC operations without increasing channel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory controller performs error detection and correction with increased ECC bits, then error correction capability is improved, but bandwidth and power consumption increase
Solution Approach 1:
The patent divides the ECC functionality into two segments: the memory device generates and stores check bits internally, while the memory controller performs error detection using these check bits. This segmentation allows the memory device to handle the computationally intensive ECC generation locally, reducing the bandwidth and power requirements for data transmission between the memory device and controller.
Solution Approach 2:
The patent introduces check bits as an intermediary element that carries error correction information between the memory device and controller. These check bits serve as a compact representation of error correction capability, allowing the system to achieve high reliability without transmitting full error correction data, thereby reducing bandwidth and power consumption.
2Reliability
If traditional memory controller performs error detection and correction with increased ECC bits, then error correction capability is improved, but data bus width must increase
Solution Approach 1:
The patent extracts the ECC bit generation and storage function from the memory controller and places it within the memory device. This extraction allows the memory controller to receive only the essential check bits for error detection, rather than requiring a widened data bus to transmit all ECC information, thus maintaining the original data bus width while improving error correction capability.
Solution Approach 2:
The patent moves the ECC functionality from the controller dimension to the device dimension, utilizing internal memory resources and processing capability within the memory device itself. This dimensional shift allows error correction capability to be enhanced without expanding the external data bus interface.
3Quantity of substance
If memory density increases with smaller feature geometries, then storage capacity is improved, but number of errors increases
Solution Approach 1:
The patent implements preliminary error correction by having the memory device generate and store check bits at the time of data writing. This preliminary action ensures that error correction capability is prepared in advance, allowing the system to maintain high reliability even as memory density increases and error rates rise due to smaller feature geometries.
Data Source
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AI summary
A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2^N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.