On-Die ECC Engine for DRAM Error Pattern Correction
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Solution Overview
Problem
The increasing bit errors and decreasing yield of dynamic random access memories (DRAMs) due to shrinking fabrication design rules pose challenges in ensuring reliable data transmission and storage.
Innovation Solution
A semiconductor memory device equipped with an on-die error correction code (ECC) engine that identifies and corrects uncorrectable errors by generating and applying error patterns to codewords, distinguishing between errors occurring during transmission and those stored in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fabrication design rules are continued to shrink to improve integration density, then productivity and integration are improved, but bit errors in memory cells rapidly increase and yield decreases
Solution Approach 1:
The patent applies preliminary action by performing ECC encoding before data is written to memory cells, and by proactively identifying and correcting uncorrectable errors before they cause data loss. The on-die ECC engine preemptively encodes parity data and continuously monitors for errors, allowing correction of errors that occur during subsequent read operations.
Solution Approach 2:
The patent implements feedback through the on-die ECC engine that continuously monitors memory cell states, identifies uncorrectable errors, and provides feedback signals to correct the errors. The system uses syndrome calculations and error pattern recognition to detect errors and adjusts data accordingly, creating a closed-loop error correction system.
2Reliability
If conventional ECC decoding is used to correct errors, then data integrity is improved, but uncorrectable errors with specific patterns cannot be identified and corrected
Solution Approach 1:
The patent applies parameter changes by modifying the ECC decoding process to include pattern recognition capabilities. Instead of only correcting random errors, the system changes the error identification parameters to recognize specific error patterns (such as burst errors or systematic errors) and adjusts correction strategies accordingly.
Solution Approach 2:
The patent performs preliminary analysis of error patterns during the decoding process, identifying uncorrectable errors before they are written back to memory. The system pre-determines error patterns and prepares correction actions in advance, allowing specialized handling of different error types.
3Reliability
If error correction operations are performed for all errors, then data integrity is improved, but processing time and energy consumption increase
Solution Approach 1:
The patent applies local quality by providing different levels of error correction for different types of errors. The system identifies the severity and pattern of errors, then applies appropriate correction measures only where needed - intensive correction for uncorrectable errors with specific patterns, and lighter correction for random errors, optimizing the balance between reliability and processing time.
Solution Approach 2:
The patent implements partial action by selectively applying error correction only to codewords that require it. The on-die ECC engine analyzes error flags and pattern recognition results to determine which errors need correction and which can be handled differently, avoiding unnecessary processing for all errors and focusing resources on critical corrections.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.