On-Die Error Control for Internal Memory Read Reliability
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Solution Overview
Problem
Memory devices often fail to detect and correct errors during internal read operations, leading to propagation and accumulation of errors, which can result in unreadable data due to the lack of error control operations within the memory device itself.
Innovation Solution
Incorporating an error control circuit on the memory die that uses a less complex decoding logic to detect and correct errors during internal read operations, while reusing the same codeword and parity bits used by the error control circuit at the memory system controller, and generating additional syndromes to reduce the risk of mis-correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error control operations are not performed during internal read operations, then device complexity is reduced, but reliability deteriorates due to error propagation and accumulation
Solution Approach 1:
The error control function is segmented into two parts: a simplified error detection circuit implemented on the memory die for internal read operations, and a more comprehensive error correction circuit at the memory system controller. This segmentation allows the memory die to perform basic error detection without the complexity of full error correction, while maintaining data integrity through the coordinated operation of both circuits.
Solution Approach 2:
Instead of implementing complete error correction functionality on the memory die, the patent applies partial error control by implementing only error detection capabilities on the die. This partial action is sufficient to identify errors during internal read operations, allowing the system to handle uncorrectable errors appropriately while avoiding the complexity of full error correction at this level.
2Device complexity
If a less complex decoding logic is used on the memory die, then device complexity is reduced, but measurement precision deteriorates in error detection capability
Solution Approach 1:
The patent introduces an intermediary mechanism where the simplified error detection circuit on the memory die works in conjunction with the more capable error correction circuit at the memory system controller. The intermediary communication between these two circuits allows the simple on-die circuit to trigger appropriate error handling actions without needing to perform complex error correction itself, thus maintaining both low complexity and high detection accuracy.
3Reliability
If additional syndromes are generated for error correction, then reliability is improved by reducing mis-correction risk, but device complexity increases
Solution Approach 1:
The syndrome generation and processing is segmented between the memory die and the memory system controller. The memory die generates a subset of syndromes using simplified logic for basic error detection, while the memory system controller performs more comprehensive syndrome analysis for accurate error correction. This segmentation reduces the complexity burden on the memory die while maintaining high error correction accuracy through the controller's more powerful processing capabilities.
Data Source
AI summary
Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.