On-Die Isolation Circuit With Variable Current Limiting for Burn-In
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor wafer-level testing methods fail to adequately isolate defective die during burn-in processes, leading to reduced supply voltage uniformity and limited testing modes due to fixed current limiting mechanisms, which can prevent reliable testing of functional die and require multiple power supplies.
Innovation Solution
The implementation of on-die isolation circuits with a variable resistor stack, controlled by enable inputs and registers, allows for dynamic current limiting during testing operations, accommodating various testing modes and isolating defective die without affecting functional die, thereby maintaining voltage uniformity and reducing the need for multiple power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external resistors or fuses are used to isolate defective die, then current limiting is achieved, but testing modes are limited due to fixed current values
Solution Approach 1:
The patent implements a variable resistor stack with multiple resistance levels that can be dynamically selected based on testing requirements. The resistor stack includes several resistors connected in series, with taps at different points along the stack allowing selection of different resistance values. This dynamic adjustment capability enables support for multiple testing modes (native testing, BIST, BISS, DFT) while maintaining a single integrated isolation circuit structure on each die.
Solution Approach 2:
The patent changes the resistance parameter of the isolation circuit by providing a resistor stack with multiple discrete resistance values. Each resistance value is optimized for specific testing modes, allowing the isolation circuit to adapt its electrical characteristics to match different testing requirements. This parameter variation enables versatile testing capabilities without requiring multiple separate isolation circuits.
2Reliability
If defective die are not isolated during burn-in, then supply voltage is maintained, but defective die draw excessive current and reduce voltage uniformity across the wafer
Solution Approach 1:
The patent extracts or removes excessive current drawn by defective die through the isolation circuit. Each die has its own isolation circuit with a variable resistor stack that limits current flow. When a die is detected as defective, the isolation circuit is activated to extract the harmful excessive current, preventing it from affecting other die on the wafer and maintaining voltage uniformity across the entire wafer during burn-in operations.
Solution Approach 2:
The isolation circuit acts as an intermediary element between the power supply and each individual die. The variable resistor stack serves as a mediator that can be adjusted to appropriate resistance values to control current flow. This intermediary structure allows defective die to be electrically isolated while still maintaining their physical connection to the wafer, enabling continued operation of functional die without interference from defective ones.
3Adaptability or versatility
If fixed current limiting is used, then simple isolation is achieved, but multiple current values needed for different testing modes cannot be provided
Solution Approach 1:
The patent segments the isolation circuit into modular components: a resistor stack divided into multiple resistors with taps at different points, and a selection mechanism that can choose between different resistance levels. This segmentation allows the circuit to provide multiple current limiting values (R1, R2, R3, etc.) while maintaining a structured and manageable design. Each segment can be independently optimized for specific testing mode requirements.
Solution Approach 2:
The variable resistor stack provides multi-functionality by serving as the isolation element for multiple different testing modes. A single resistor stack structure with selectable taps can accommodate native testing, BIST, BISS, and DFT modes, each requiring different current values. This universal design eliminates the need for separate isolation circuits for each testing mode, reducing overall device complexity while enhancing adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient and reliable testing of all die on a wafer, even with defective die present, by dynamically controlling current and preventing voltage drops, thus reducing manufacturing costs and improving testing efficiency.
Implementation Method 1
a resistor connected to a source of the first transistor. A register is connected to the drain of the first transistor. A second transistor is in parallel with the resistor
Data Source
AI summary
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register.