On-Die Jitter Tolerance Testing with Phase-Shifted Clock Sampling
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Solution Overview
Problem
Jitter tolerance tests are challenging to perform accurately and efficiently, especially on incomplete chips during production or assembly, due to the need for expensive equipment and difficulty in accessing high-speed test points.
Innovation Solution
A system and method for on-die jitter tolerance testing using generated clocks with specific phase shifts to assess jitter tolerance, allowing for cheaper and more convenient evaluation of electrical components by determining the eye opening of input data through phase-shifted clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If jitter tolerance tests are performed in a lab environment with expensive equipment, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements built-in self-test functionality where the device under test performs jitter tolerance measurements on itself using integrated test circuits and logic. The device generates test signals, applies jitter, and measures its own tolerance without requiring external expensive test equipment, thereby resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The test circuit is designed to perform multiple functions including signal generation, jitter injection, and tolerance measurement within a single integrated structure. This multi-functional approach eliminates the need for separate specialized equipment while maintaining measurement accuracy, addressing the contradiction between precision and complexity
2Productivity
If jitter tolerance tests are performed on incomplete chips during production, then productivity is improved, but ease of operation deteriorates due to difficulty in accessing test points
Solution Approach 1:
The test circuit is fully integrated within the chip, allowing the incomplete chip to perform self-testing without requiring access to external high-speed test points. The internal test logic generates and measures signals within the chip boundaries, making testing feasible during production before the chip is fully assembled
Solution Approach 2:
The patent moves the test functionality from external dimension (requiring access to chip package test points) to internal dimension (within the chip substrate). By implementing the test circuit at the die level, the system enables testing in a different spatial dimension where accessibility is not constrained by package assembly status
3Measurement precision
If phase-shifted clock signals are used to assess jitter tolerance, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent measures jitter tolerance by varying the phase shift parameter of clock signals relative to the data signal. By changing this single parameter (phase offset) and observing when sampling errors occur, the system accurately determines eye opening without requiring complex measurement circuits. The phase shift is controlled through simple delay elements or phase-locked loops already present in the device
Data Source
AI summary
A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.