On-Die Memory Mirroring for DRAM Reliability
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Solution Overview
Problem
As Dynamic Random Access Memory (DRAM) is miniaturized, cell characteristics deteriorate, leading to increased cell defects and memory failures, which are critical issues in applications like data centers and autonomous vehicles, where single or multi-bit errors can cause system halts or abnormal data processing, and existing channel mirroring operations compromise performance and capacity.
Innovation Solution
A memory system employing an on-die mirroring technique that simultaneously writes data to a first and second memory area in response to a single address, allowing for read retry operations from the second area when errors exceed a reference value, thereby maintaining reliability without decreasing performance or capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel mirroring operation is applied to improve reliability, then data reliability is improved, but memory capacity and performance decrease
Solution Approach 1:
The memory device is divided into two distinct memory areas: a first memory area for normal data storage and a second memory area for mirrored data storage. This segmentation allows the system to maintain full memory capacity while enabling reliability improvements through selective mirroring of specific data portions, rather than requiring channel-level mirroring that reduces performance.
Solution Approach 2:
The patent introduces a new dimension of operation by implementing mirroring at the memory device level rather than at the channel level. This dimensional change allows the system to achieve reliability benefits without the performance penalties associated with traditional channel mirroring, as the mirroring operation occurs within the memory device itself through dual memory area utilization.
2Reliability
If channel mirroring operation is applied to improve reliability, then data reliability is improved, but memory capacity decreases
Solution Approach 1:
The memory device is divided into two distinct memory areas: a first memory area for normal data storage and a second memory area for mirrored data storage. This segmentation allows the system to maintain full memory capacity while enabling reliability improvements through selective mirroring of specific data portions, rather than requiring channel-level mirroring that reduces performance.
Solution Approach 2:
The second memory area serves multiple functions: it acts as a mirror for reliability protection during normal operation, and can be activated as an alternative data path when errors are detected in the first memory area. This multi-functionality ensures that the full memory capacity remains available while providing reliability benefits through the mirrored portion.
3Reliability
If on-die mirroring is implemented to maintain reliability, then data reliability is maintained, but device complexity increases
Solution Approach 1:
The patent merges the reliability protection function directly into the memory device structure by integrating the second memory area and error detection logic within the same device. This consolidation eliminates the need for separate channel-level mirroring hardware, reducing overall system complexity while maintaining reliability benefits through on-die mirroring capability.
Data Source
AI summary
A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.