On-Die Termination Circuit Using Delay-Based Impedance Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional on-die termination circuits face impedance mismatching issues due to differences in the manufacturing of PMOS transistors, leading to offset voltages and ineffective impedance matching, which result in signal reflection.
Innovation Solution
An on-die termination circuit that includes a reference period signal generator, a first period signal generator, a period comparator, and a driver, which compares the periods of the generated signals to adjust the resistance values and achieve impedance matching without relying on a comparator, thereby reducing abnormal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a comparator is used to compare pad voltage with reference voltage, then impedance matching can be achieved, but manufacturing variations in PMOS transistors cause offset voltages that prevent accurate comparison
Solution Approach 1:
The patent extracts and removes the comparator component from the impedance matching circuit. Instead of using a comparator to compare voltages, the invention uses a delay element to compare signal delays, thereby eliminating the source of offset voltage errors caused by PMOS transistor manufacturing variations.
Solution Approach 2:
The patent replaces the electrical voltage comparison mechanism with a temporal delay comparison mechanism. Instead of comparing voltage levels electrically through a comparator, the system compares the time delays of signals passing through different paths, substituting an electrical measurement system with a temporal measurement system that is immune to PMOS variation effects.
2Measurement precision
If offset voltage is generated due to PMOS transistor size differences, then the comparison result becomes inaccurate, but increasing PMOS size matching is difficult due to manufacturing process limitations
Solution Approach 1:
The invention removes the comparator that requires matched PMOS transistors from the circuit. By extracting this component, the design eliminates the manufacturing constraint of matching PMOS sizes while maintaining measurement accuracy through delay-based comparison.
Solution Approach 2:
The patent changes the comparison parameter from voltage level to time delay. This parameter transformation allows the system to achieve accurate impedance matching without requiring precise PMOS transistor size matching, as delay comparison is not affected by transistor size variations in the same way voltage comparison is.
3Reliability
If the resistance value of the driver is changed to match external resistance, then impedance matching is achieved, but signal reflection occurs when offset voltage causes incorrect comparison
Solution Approach 1:
The patent replaces the voltage comparison mechanism with a delay comparison mechanism. This substitution ensures that the driver resistance adjustment is based on accurate delay measurements rather than offset-prone voltage comparisons, thereby preventing signal reflection caused by incorrect impedance matching decisions.
Solution Approach 2:
The system uses delay comparison results as feedback to adjust the driver resistance value. By implementing feedback based on accurate delay measurements rather than offset-affected voltage comparisons, the system reliably achieves impedance matching and prevents signal reflection.
Data Source
AI summary
An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.