On-Die Termination Switching for Shared-Pad Memory Dice
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In non-volatile memory systems, signal reflections caused by impedance discontinuities in high-frequency operations degrade signal integrity, which existing technologies fail to adequately address by providing a single ODT configuration for both target and non-target memory dice.
Innovation Solution
The implementation of a method to configure on-die termination circuits in each memory die, where each die determines whether it is a target or non-target, and sets a corresponding on-die termination configuration value to provide different termination resistances, thereby improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ODT configuration is used for both target and non-target memory dice, then device complexity is reduced, but signal integrity deteriorates due to impedance discontinuities and signal reflections
Solution Approach 1:
The patent applies local quality by configuring different ODT values for different memory dice based on their specific roles. Target memory dice use a first ODT configuration while non-target memory dice use a second ODT configuration, optimizing signal integrity for each die's specific function in the memory system
Solution Approach 2:
The patent segments the memory system into target and non-target memory dice, with each segment receiving a customized ODT configuration. This segmentation allows independent optimization of termination resistance for each group, improving overall signal integrity without requiring a single complex configuration
2Reliability
If different ODT configurations are used for target and non-target memory dice, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic ODT configuration where memory dice can switch between different ODT states based on their operational role. The first and second ODT configurations are selectively applied depending on whether a die is acting as a target or non-target, allowing adaptive optimization without permanent complexity
Solution Approach 2:
The patent changes the termination resistance parameter based on the memory die's role. By adjusting the ODT configuration parameter (first ODT value vs. second ODT value), the system optimizes signal characteristics for different operational scenarios without fundamentally changing the hardware architecture
3Productivity
If high-frequency operations are performed in memory systems, then productivity is improved, but signal reflections and impedance discontinuities worsen
Solution Approach 1:
The patent applies preliminary action by pre-configuring appropriate ODT values for target and non-target memory dice before high-frequency operations begin. This preliminary configuration establishes proper impedance matching in advance, preventing signal reflections before they occur during high-speed data transfer
Solution Approach 2:
The patent implements preliminary anti-action by applying termination resistance through ODT configurations before signals can reflect off impedance discontinuities. The first and second ODT configurations are set in advance to counteract potential signal reflections, allowing high-frequency operations to proceed with maintained signal integrity
Data Source
AI summary
A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value