On-Die Termination Switching for High-Speed Memory Write Signals
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Solution Overview
Problem
High-speed signaling systems with single-termination schemes experience sub-optimal performance due to impedance discontinuity and signal attenuation, leading to reduced signaling margins and increased error rates.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load and low-load terminations based on whether the memory module is the destination for incoming signals, to achieve optimal load-matching and energy absorption without attenuating incoming signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-termination structures are used on high-speed signaling lines, then device complexity is reduced, but signaling margins deteriorate due to impedance discontinuity and signal attenuation
Solution Approach 1:
The patent divides the termination structure into multiple segmented termination circuits, each with its own switch element and load element. These segments can be independently controlled to provide different termination impedances at different locations along the signal line, resolving the contradiction by maintaining simple individual segments while achieving complex overall termination behavior that improves signaling margins
Solution Approach 2:
The patent implements dynamic termination control where switch elements can dynamically connect or disconnect load elements based on operational conditions. This allows the termination impedance to be adjusted in real-time to match different signal line conditions, improving signaling margins while maintaining simple static structure when dynamic adjustment is not needed
2Object-generated harmful factors
If termination load is increased to improve load-matching, then reflections are reduced, but signal attenuation increases
Solution Approach 1:
The patent applies different termination load values at different locations along the signal line based on local impedance requirements. Load elements with different resistance values can be selectively activated to provide optimal local matching, reducing reflections at specific points without unnecessarily increasing attenuation across the entire signal path
Solution Approach 2:
The patent changes the termination impedance parameter dynamically by switching between different load elements with different resistance values. This allows the termination impedance to be optimized for specific operating conditions, achieving effective reflection cancellation only when needed while minimizing signal attenuation during other operations
Data Source
AI summary
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.