On-Die Timer Shadowing for Accurate Low-Power State Recovery
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Solution Overview
Problem
Existing power management standards like ACPI do not optimize power consumption or performance for specific data processing systems, leading to inefficiencies in power-saving modes and potential operational errors due to inaccurate timer restoration in non-operational power states.
Innovation Solution
Implementing a power state controller with a shadow timer mechanism that adjusts and synchronizes clock frequencies to accurately restore timer values during power state transitions, using a cross-domain synchronization circuit to minimize errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If devices are put into non-operational power-saving modes, then power consumption is reduced, but timer accuracy deteriorates due to clock signal loss
Solution Approach 1:
The system performs preliminary actions by saving timer values and clock frequency information before entering the non-operational power state. This allows the timer to be accurately restored later without maintaining continuous clock operation, thus reducing power consumption while preserving timer accuracy.
Solution Approach 2:
The invention creates a copy of the timer value and clock frequency state before entering low-power mode. This copied information is stored and used to restore the timer accurately after waking up, eliminating the need to maintain the original timer operation during power-saving states.
2Loss of energy
If clock frequency is adjusted for power saving, then power consumption is reduced, but timer restoration accuracy deteriorates due to frequency differences
Solution Approach 1:
The system uses feedback by monitoring the clock frequency and using this information to calculate the appropriate adjusted timer value. The restored timer value compensates for the frequency difference, ensuring accurate timer restoration even when clock frequency changes occur during power state transitions.
Solution Approach 2:
The invention changes the timer parameter (timer value) based on the clock frequency change. By adjusting the timer value according to the frequency ratio between operational and non-operational states, the system maintains timer accuracy despite operating at different clock frequencies during power-saving modes.
3Adaptability or versatility
If standard power management is used, then system compatibility is improved, but power optimization for specific systems deteriorates
Solution Approach 1:
The system applies local quality by implementing specific power management optimizations for particular circuits and devices within the system. While maintaining overall ACPI compatibility, the invention allows individual components to use optimized power states and timer management tailored to their specific characteristics, achieving better power efficiency without sacrificing system-wide compatibility.
Data Source
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AI summary
An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.