On-Die Voltage Comparison Circuit for Non-Destructive Current Mapping
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Solution Overview
Problem
Current methods for analyzing transistor mismatches in integrated circuits are time-consuming and destructive, limiting the ability to collect comprehensive current measurement data across dies, which hampers yield improvement efforts.
Innovation Solution
A comparison circuit with a current-to-clock circuit that allows for non-destructive measurement of currents across integrated circuit dies by converting input currents into output clocks with frequencies proportional to the input currents, enabling high spatial granularity and efficient data collection without altering the silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical failure analysis operations are performed to delayer metal layers and build probe pads to access transistors, then current measurements can be obtained for transistor mismatch analysis, but the process is time-consuming (taking a week or longer per die) and destructive to the circuitry
Solution Approach 1:
Test matched devices are fabricated in advance during the manufacturing process in empty areas or scribe lines of the wafer. Access paths and pad structures are pre-configured so that when a mismatch is detected, the location is already known and accessible, eliminating the need for time-consuming delayering and probe pad construction later.
Solution Approach 2:
Instead of physically modifying the actual circuitry to access transistors, the invention uses test matched devices that are copies or replicas of the actual circuit elements. These test devices are located in accessible areas and provide the same electrical characteristics, allowing measurements without damaging the production dies.
2Measurement precision
If physical failure analysis operations are performed to access transistors, then current measurements can be collected, but the destructive nature of the process prevents analyzing more than a handful of dies
Solution Approach 1:
The wafer is segmented into functional circuit areas and test/analysis areas. Test matched devices are placed in empty areas or scribe lines separate from the production circuitry. This segmentation allows test operations to be performed on test devices without affecting or destroying the production dies, enabling analysis of multiple dies.
Solution Approach 2:
Test matched devices serve as intermediaries between the measurement system and the actual transistors. These intermediary test devices are electrically equivalent to the production transistors but are located in accessible areas with pre-built pad structures, allowing measurements to be taken without directly accessing or damaging the production circuitry.
3Ease of manufacture
If test matched devices are fabricated in empty areas or scribe lines, then current measurements can be performed with pre-built access pads, but the spatial granularity is relatively low and cannot provide visibility into intra-die process variations
Solution Approach 1:
Different regions of the wafer are assigned different functions with different levels of access. Production circuit areas maintain their original high-density layout optimized for manufacturing, while test matched devices are placed in empty areas or scribe lines with optimized test access. This local differentiation allows each region to serve its primary purpose while providing complementary capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient determination of current measurements across many pairs of transistors at high spatial granularity without damaging the dies, reducing analysis time and maintaining yield, as current measurements can be obtained through existing pads without physical failure analysis.
Implementation Method 1
a comparison capacitor having a first terminal that is coupled to both a first terminal of a first switch and a first terminal of a second switch and having a second terminal that is coupled to both a first terminal of a third switch and an input of an inverter
Data Source
AI summary
In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.