One-Bit Neural Cell Architecture for Low-Power IoT Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IoT devices require high-power software implementations for simulated neural networks, which is inefficient due to the lack of hardware architectures that effectively utilize the parallel nature of neural networks.
Innovation Solution
A digital neural network architecture with multiple layers of neural cells, each containing one-bit inputs, an adder and leaky integrator unit, and an activation function circuit, which calculates a leaky integral and applies an activation function to generate a one-bit output, optimized for ultra-low power consumption and implemented without multipliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If software implementation of neural networks is used on general-purpose platforms, then neural network processing can be performed, but power consumption is high
Solution Approach 1:
The patent replaces software-based neural network processing with a dedicated hardware architecture. The neural network is implemented using physical neural cells with analog components (capacitors for integration, resistors for weighting) that naturally perform neural computations through electrical signals, eliminating the need for software interpretation and reducing power consumption while improving processing efficiency.
Solution Approach 2:
The hardware architecture uses universal neural cell units that can be configured to perform different neural network operations. Each neural cell can be programmed with different weights and thresholds, allowing the same physical hardware to implement various neural network models and functions, achieving both low power consumption and high processing efficiency.
2Use of energy by moving object
If hardware architectures are used to implement neural networks, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The neural network hardware is segmented into identical, modular neural cell units. Each cell is a self-contained module with standardized inputs, outputs, and internal components. This segmentation allows complex neural networks to be built by replicating simple cell units, reducing individual cell complexity while enabling scalable system complexity.
Solution Approach 2:
The patent implements a hierarchical structure where neural cells are nested within layers, which are nested within the complete neural network. Each neural cell contains nested sub-components (capacitors, resistors, transistors) organized in a standardized configuration. This nesting allows complex network functionality to emerge from simple, repeating units.
3Measurement precision
If multipliers are used in neural network implementation, then computation accuracy is improved, but silicon area usage and power consumption increase
Solution Approach 1:
The patent replaces expensive, power-consuming multipliers with simpler, lower-power computational elements. Weighted inputs are implemented using resistor-based voltage division and capacitor-based integration, which provide sufficient accuracy for neural network operations while consuming significantly less power and occupying less silicon area than traditional multiplier circuits.
Solution Approach 2:
The patent changes the computational approach from digital multiplication to analog integration. By using continuous voltage signals and capacitive integration, the system achieves accurate computation of weighted sums without requiring complex multiplier circuits, thereby reducing power consumption and silicon area while maintaining computation accuracy.
Data Source
AI summary
A neural network that may include multiple layers of neural cells; wherein a certain neural cell of a certain layer of neural cells may include a first plurality of one-bit inputs; an adder and leaky integrator unit; and an activation function circuit that has a one-bit output; wherein the first plurality of one-bit inputs are coupled to a first plurality of one-bit outputs of neural cells of a layer that precedes the certain layer; wherein the adder and leaky integration unit is configured to calculate a leaky integral of a weighted sum of a number of one-bit pulses that were received, during a time window, by the first plurality of one-bit inputs; and wherein the activation function circuit is configured to apply an activation function on the leaky integral to provide a one-bit output of the certain neural cell.