One-Direction Error Recovery Flow for Skew Data Corruption
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Solution Overview
Problem
Conventional memory sub-systems fail to identify and remedy skew data corruption (SDC) caused by corruptive reads, leading to high raw bit error rates and compromised Quality of Service (QoS) due to unmanaged partial writes, which result in extra error recovery handling and performance degradation.
Innovation Solution
Implementing a one-direction error recovery flow (ERF) that adjusts read voltage levels in the opposite direction of a partial write to successfully decode data and perform a refresh write operation when the directional error bit count exceeds a threshold, thereby minimizing SDC and reducing error recovery handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory sub-systems perform read operations without voltage adjustment, then read speed is maintained, but skew data corruption occurs due to corruptive reads
Solution Approach 1:
The system dynamically adjusts read voltage levels based on detected partial write conditions. When skew data corruption is identified through error bit count analysis, the read voltage is adjusted in a first direction to compensate for the partial write effect, transforming a static read operation into a dynamic, adaptive process that maintains both speed and reliability
Solution Approach 2:
The system implements a feedback mechanism where error bit counts from read operations are analyzed to detect partial writes. This feedback triggers voltage adjustment in subsequent reads, creating a closed-loop control system that continuously monitors and corrects for skew data corruption while maintaining optimal read performance
2Reliability
If error recovery handling is performed for all read errors, then data reliability is improved, but performance degradation occurs due to extra handling overhead
Solution Approach 1:
The system applies different error handling strategies based on the specific error characteristics detected. Instead of uniform error recovery for all reads, it selectively adjusts voltage only for reads exhibiting partial write patterns (specific error bit count distributions), applying quality control locally where needed rather than globally, thus maintaining performance while improving reliability
Solution Approach 2:
The system changes operational parameters (read voltage level) based on error analysis results. When specific error patterns indicating partial writes are detected, the read voltage parameter is adjusted for subsequent operations, allowing the system to adapt to error conditions and reduce unnecessary full error recovery handling, thereby maintaining performance
3Reliability
If read voltage level is adjusted to compensate for partial write, then skew data corruption is reduced, but additional voltage adjustment operations increase complexity
Solution Approach 1:
The system performs preliminary analysis of error bit counts from initial read operations to detect partial write conditions before they cause significant corruption. By identifying and compensating for partial writes early through voltage adjustment, the system prevents skew data corruption from escalating, reducing the need for more complex remedial actions later
Solution Approach 2:
The system replaces complex mechanical or hardware-based error correction mechanisms with a software-controlled voltage adjustment approach. By using controller logic to analyze error patterns and adjust read voltage levels, the system achieves skew data corruption mitigation through intelligent control rather than complex physical mechanisms, reducing overall device complexity
Data Source
AI summary
Described herein are embodiments related to one-direction error recovery flow (ERF) operations on memory components of memory systems. A processing device determines that data from a read operation is not successfully decoded because of a partial write of the data. The partial write results from a number of memory cells written as a first state and read as a second state. The processing device performs a one-direction ERF on the memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded. The first direction corresponds to an opposite direction of a state shift of the partial write. The processing device can also can determine a directional EBC and perform a refresh write if necessary.