One-Hot Clock Control for Scan Test Coverage
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Solution Overview
Problem
Scan tests on electronic circuits often result in timing violations and ambiguous signal values ('X') due to asynchronous crossings, leading to test coverage loss and increased test time, especially when hardware compression mechanisms are used, as they corrupt other scan out signals.
Innovation Solution
The implementation of programmable DFT overrides on local clock gates allows for fine-tuned clock control by generating one-hot signals for each clock domain, enabling independent control of capture clock pulses and reducing the need for additional test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware compression mechanisms (MISR, XOR trees) are used to compress test responses, then test time is reduced and bandwidth is minimized, but any X value in scan out signals corrupts all other scan outs in the same compression cone, causing significant test coverage loss
Solution Approach 1:
The patent segments the clock control by introducing one-hot encoded clock control signals that independently control different clock domains. This segmentation prevents X values from propagating across entire compression cones by isolating clock control to specific domains, thereby maintaining test coverage while using hardware compression.
Solution Approach 2:
The patent applies preliminary action by setting up one-hot encoded clock control patterns before test compression is applied. By pre-configuring which clock domains are active through one-hot encoding, the system prevents X value corruption before it can affect the compressed test results, preserving both test time efficiency and coverage reliability.
2Ease of operation
If OCC flip-flops are used to control clock pulsing at the clock root, then coarse clock control is achieved, but fine-tuned control of individual clock domains is not possible, leading to asynchronous crossings and X values
Solution Approach 1:
The patent segments the coarse OCC clock control into fine-grained one-hot encoded clock control signals for individual clock domains. This segmentation enables independent control of each clock domain, preventing asynchronous crossings between domains and eliminating X values while maintaining ease of operation through systematic encoding.
Solution Approach 2:
The patent applies local quality by providing dedicated one-hot encoded clock control signals to each local clock gate in different clock domains. This allows each clock domain to have its own controlled clock pulsing independent of others, ensuring signal value accuracy while maintaining overall system ease of operation through unified one-hot encoding methodology.
3Reliability
If additional test patterns are applied to recover coverage loss from X values, then test coverage is improved, but test time increases significantly
Solution Approach 1:
The patent applies preliminary action by establishing one-hot encoded clock control patterns before test compression is applied. By pre-configuring which clock domains are active through one-hot encoding, the system prevents X value corruption before it can affect the compressed test results, preserving both test time efficiency and coverage reliability.
4Device complexity
If the same OCC controls all logic in a clock domain group, then device complexity is reduced, but fine-tuned clock control for functionally asynchronous logic is not achievable, causing asynchronous crossings
Solution Approach 1:
The patent segments the unified OCC clock control into domain-specific one-hot encoded control signals for individual clock domains. This segmentation enables independent control of each clock domain without significantly increasing device complexity, as the one-hot encoding provides a systematic and efficient control mechanism that prevents asynchronous crossings while maintaining manageable complexity.
Data Source
AI summary
A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.