One-Hot Speculative DFE for High-Speed Receiver ISI Cancellation
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Solution Overview
Problem
Traditional Decision Feedback Equalizers (DFEs) face limitations in achieving power and area efficiency for high data rate input-output links due to complexity and exponential power and area costs, making them unsuitable for ultra-high data rates like 60 Gb/s and beyond, especially when dealing with Inter-Symbol-Interference (ISI).
Innovation Solution
The implementation of a low power, high-speed receiver using a 1-hot speculative DFE with a modified Mueller-Muller clock and data recovery system, which constrains the first post-cursor ISI of PAM signals to half the cursor magnitude, reducing the number of samplers required and implementing 1-hot encoding to reduce critical loop timing by 50% compared to traditional speculative DFEs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional DFE is used for ISI removal at high data rates, then ISI cancellation capability is provided, but propagation delay of closed loop components (summer, sampler, delay unit, weight multiplier) limits the achievable data rate
Solution Approach 1:
The patent applies preliminary action by performing speculative DFE tap selection in advance before the actual data decision is made. Multiple potential tap values are pre-calculated and stored, allowing the equalizer to quickly select the appropriate tap without waiting for the full decision loop to complete. This preliminary computation enables higher data rates by reducing the critical path delay of the DFE loop.
2Speed
If DFE with tap speculation is used to improve data rate and channel loss tolerance, then data rate increases, but exponential power and area cost makes it unattractive for power and area efficient links
Solution Approach 1:
The patent applies local quality by implementing selective tap speculation only for specific cursor positions and data patterns where it provides the most benefit. Instead of speculating all taps uniformly, the invention identifies and applies speculation selectively to the most critical taps (e.g., first post-cursor) and specific data patterns (e.g., transitions), thereby reducing overall power consumption while maintaining data rate improvements.
3Speed
If DFE with tap speculation is used to improve data rate and channel loss tolerance, then data rate increases, but exponential area cost makes it unattractive for area efficient links
Solution Approach 1:
The patent applies segmentation by dividing the DFE tap speculation into separate, independent modules for different cursor positions and data patterns. Each segment handles a specific tap position or pattern type, allowing parallel implementation without full exponential growth. This modular segmentation reduces the overall circuit area by avoiding redundant computation across all possible tap combinations.
4Reliability
If traditional DFE is used, then ISI removal is achieved, but the closed loop propagation delay prevents feasibility at ultra-high data rates of 60 Gb/s and more
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing speculative tap values before they are needed for the actual equalization decision. This allows the critical DFE loop to use pre-prepared values without undergoing the full computation cycle, thereby maintaining reliable ISI cancellation while achieving the ultra-high data rates of 60 Gb/s and beyond that would otherwise be impossible due to propagation delay constraints.
Data Source
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AI summary
Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1-hot encoded data.