One-Piece Conductive Pillar Structure for Stress-Resistant Chip Interconnects
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes due to reduced feature sizes, which affects the reliability and efficiency of semiconductor integrated circuits.
Innovation Solution
A chip structure is developed with conductive pillars and conductive via structures, utilizing thick metal wiring layers and conductive lines to enhance stability and reduce stress migration, combined with a specific formation process involving deposition, etching, and plating to create a robust interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and reliability deteriorate
Solution Approach 1:
The patent segments the conductive interconnect structure into multiple distinct layers: a first conductive layer with via structures, a second conductive layer with pillar structures, and intermediate dielectric layers. This segmentation allows each layer to be optimized independently for its specific function, maintaining reliability while enabling continued scaling for higher productivity.
Solution Approach 2:
The patent employs composite material structures by combining different conductive materials (copper, cobalt, tungsten) and dielectric materials (silicon oxide, silicon nitride) in a multi-layer interconnect system. Each material is selected for its specific properties to address reliability concerns at reduced feature sizes while maintaining manufacturing efficiency.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: forming via structures in the first dielectric layer, forming pillar structures in the second dielectric layer, and establishing electrical connections between them. This segmentation simplifies the overall fabrication complexity by breaking down the complex interconnect formation into manageable, standardized processes that can be executed with existing manufacturing capabilities.
3Ease of manufacture
If conventional conductive structures are used at reduced feature sizes, then manufacturing simplicity is maintained, but stress migration and electromigration increase
Solution Approach 1:
The patent uses composite material structures where copper interconnects are combined with cobalt barrier layers and tungsten plug structures. This composite approach provides both manufacturing compatibility (using standard deposition and etching processes) and enhanced reliability through materials selected for their resistance to stress migration and electromigration at reduced feature sizes.
Solution Approach 2:
The patent incorporates barrier layers (such as cobalt) and isolation dielectric structures beforehand to protect the conductive interconnects from stress migration and electromigration. These protective structures are formed in advance during the fabrication process to cushion against reliability degradation before the devices begin operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure improves the reliability and efficiency of semiconductor devices by reducing stress migration and electromigration, allowing for more reliable electrical connections and increased layout flexibility.
Implementation Method 1
a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, and the conductive pillar is in direct contact with the first conductive line
Implementation Method 2
a specific formation process involving deposition, etching, and plating to create a robust interconnect structure
Implementation Method 3
a specific formation process involving deposition, etching, and plating to create a robust interconnect structure
Data Source
AI summary
A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.