One-Port RAM Control Circuit for Dual-Port Arbitration
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Solution Overview
Problem
Conventional semiconductor storage devices lack a full dual-port configuration, leading to complex circuitry and inefficient power management, particularly in portable devices where asynchronous access and low-speed clocking are necessary to reduce power consumption.
Innovation Solution
A semiconductor storage device is created by adding a simplified control circuit to a general one-port RAM, which includes a selection circuit and a control circuit with phase adjustment, phase comparison, and selection sections to arbitrate access requests from two ports, allowing asynchronous access and converting clock signals to prevent conflicts, effectively utilizing a one-port RAM as a full two-port RAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a full dual-port configuration is implemented using conventional methods, then both ports can access memory simultaneously, but the circuit complexity increases significantly
Solution Approach 1:
The patent applies universality by enabling a single-port RAM to perform dual-port functions through a control circuit that arbitrates between two ports. The same memory circuit serves both port A and port B, with the control circuit dynamically assigning access rights based on arbitration results, thus making the memory system multi-functional without duplicating hardware resources.
Solution Approach 2:
The control circuit acts as an intermediary between the two ports and the memory circuit. It receives access requests from both ports, arbitrates them according to priority rules, and controls the selection circuit to grant access to the winning port. This mediator approach avoids the complexity of simultaneous dual-port access by sequentializing access through intelligent control.
2Use of energy by moving object
If asynchronous access with low-speed clocking is used to reduce power consumption, then power consumption decreases, but access speed and productivity are reduced
Solution Approach 1:
The patent applies dynamics by implementing a dynamic arbitration mechanism that adapts to the timing characteristics of asynchronous access requests from two different clock domains. The control circuit dynamically determines access priority based on the phase relationship between clock signals, allowing the system to optimize between power consumption and access speed by selecting appropriate arbitration strategies based on real-time conditions.
Solution Approach 2:
The patent utilizes periodic action through the use of clock signals with different phases to control access timing. By aligning access requests with specific phases of the clock cycles, the system can efficiently manage asynchronous access patterns while maintaining power efficiency. The periodic clocking provides a structured framework for managing access timing without requiring high-speed continuous operation.
3Adaptability or versatility
If different clock speeds are used for CPU and image processing systems, then each system can operate at optimal speed, but timing conversion and arbitration become more complex
Solution Approach 1:
The patent applies asymmetry by designing the arbitration logic to inherently handle asymmetric clock domains. The control circuit uses the phase difference between clock signals as a natural timing reference, creating an asymmetric arbitration scheme where priority assignment depends on clock phase relationships. This asymmetric approach simplifies timing conversion by leveraging the existing clock asymmetry rather than trying to synchronize the domains.
Solution Approach 2:
The patent utilizes parameter changes by varying the arbitration criteria based on clock signal parameters such as phase and frequency. The control circuit monitors clock parameters and adjusts arbitration behavior accordingly, allowing the system to adapt to different clock speed combinations. This parameter-based control enables flexible timing conversion without requiring complex fixed timing logic.
Data Source
AI summary
A semiconductor storage device has a simple control circuit that is added to a general one-port RAM. Taking a port-A clock signal as the reference, the control circuit generates a select signal that selects a port A during the period from elapse of a first predetermined time from the reference timing until a second predetermined time has elapsed and selects a port B during other periods. The control circuit generates a port-A delayed clock signal in the period in which the port A is selected. The control circuit generates a port-B delayed clock signal during the period from elapse of the second predetermined time until a third predetermined time has elapsed. The control circuit generates a conflict monitoring signal during the period from the reference timing until the second predetermined time has elapsed. When a clock signal is supplied from the port B while the conflict monitoring signal is being generated, the port-B delayed clock signal is masked while the conflict monitoring signal is being generated. After the conflict monitoring signal is stopped, the B-port delayed clock signal is generated as a port-B clock signal.