One-Transistor Memory Cell With Gate-Controlled Diode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory cells face challenges in achieving high density and performance, with DRAM cells being slow and requiring large capacitors, while SRAM cells have high standby power consumption and complex fabrication processes, and existing solutions like NDR devices suffer from low speeds and high voltages.
Innovation Solution
The development of memory cells with a single transistor and an integrated diode having an intrinsic region, which replaces the capacitor and provides DRAM-like density and SRAM-like performance, using gate-controlled diodes for enhanced speed and reduced power consumption, and leveraging SOI technology for improved operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM cell design is used to achieve high density, then cell density is improved, but operation speed deteriorates
Solution Approach 1:
The patent extracts the capacitor component from the traditional DRAM cell structure, replacing it with a single transistor that uses its channel charge to store memory states. This eliminates the need for separate capacitor structures while maintaining high density through the simplified one-transistor design.
Solution Approach 2:
The invention changes the fundamental operating parameters by utilizing the transistor's channel charge distribution rather than voltage storage in a capacitor. This parameter shift enables both high density through compact transistor structures and faster operation through direct charge manipulation in the channel.
2Speed
If SRAM cell design is used to achieve high performance, then operation speed is improved, but cell area increases
Solution Approach 1:
The patent removes the complex multi-transistor SRAM structure and extracts only the essential charge storage function, implementing it in a single transistor. This drastic simplification reduces cell area from 50-100F2 to a much smaller footprint while preserving fast SRAM-like operation speeds.
Solution Approach 2:
The single transistor serves multiple functions simultaneously: it acts as the access transistor, the storage element, and the switching device. This self-service approach eliminates the need for separate components required in SRAM, achieving high performance with minimal area.
3Quantity of substance
If conventional DRAM capacitor structure is used, then memory density is improved, but fabrication complexity increases
Solution Approach 1:
The patent extracts and removes the capacitor structure entirely from the memory cell design. By replacing the capacitor with a transistor-based charge storage mechanism, the fabrication process is simplified while maintaining high memory density through the compact one-transistor cell structure.
Solution Approach 2:
The invention merges the storage function previously performed by the capacitor into the transistor structure itself. The transistor's channel charge serves as the memory storage medium, combining what were previously separate components into a single integrated element that simplifies fabrication.
4Device complexity
If NDR devices are used to reduce elements per memory cell, then device count is reduced, but standby power consumption increases
Solution Approach 1:
The patent employs a conventional transistor structure that can be rapidly switched on and off, effectively using short-lived charge states for storage. This approach avoids the high standby power of NDR devices while achieving element reduction through the single-transistor design.
Solution Approach 2:
The invention changes the operational parameters by using standard transistor switching characteristics rather than relying on NDR effects. This parameter change eliminates the need for special NDR devices while maintaining low element count and reducing standby power consumption through conventional transistor operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high-density, high-performance memory cells with improved scalability, faster operation, and reduced standby power, bridging the requirements of DRAM and SRAM applications.
Implementation Method 1
The intrinsic region holds the potential of the floating node and thereby the memory state of the memory cell
Data Source
AI summary
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.