One-Transistor Multi-Capacitor Memory for Smaller Footprint
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Solution Overview
Problem
Conventional 1T-1C memory cells using ferroelectric materials face limitations in active memory layers and memory density, and fabrication challenges, particularly in achieving high density and reducing footprint area.
Innovation Solution
Implementing memory arrays with one access transistor for multiple hysteretic capacitors, utilizing a 3D stacked architecture with hysteretic capacitors and platelines in different layers, allowing for increased memory density and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 1T-1C memory cells are used, then fabrication is simpler, but memory density is limited and footprint area is larger
Solution Approach 1:
The patent implements a 3D stacked architecture where multiple memory layers are vertically stacked above a common bitline. Each memory layer contains hysteretic capacitors at different vertical positions (e.g., first layer at higher position, second layer at lower position), enabling memory cells to be stacked in the vertical dimension rather than only expanding in the horizontal plane. This dimensional transition directly increases memory density while reducing the footprint area occupied by each memory cell.
2Quantity of substance
If more memory layers are added, then memory density increases, but fabrication complexity increases
Solution Approach 1:
The patent employs a shared bitline structure that serves multiple memory layers simultaneously. The common bitline is coupled to capacitor electrodes across different vertical layers through selective coupling mechanisms, allowing a single bitline to perform read/write operations for multiple layers. This multi-functional approach reduces the number of separate bitlines needed, thereby simplifying the fabrication process while maintaining high memory density across multiple layers.
Solution Approach 2:
The patent divides the memory structure into distinct vertical layers with separated capacitor electrodes at different heights. Each layer can be independently formed and processed, allowing modular fabrication. The segmentation of capacitor electrodes into first and second layers with different vertical positions enables staged manufacturing processes, reducing overall fabrication complexity compared to forming all memory elements in a single complex step.
3Quantity of substance
If 3D stacked architecture is implemented, then memory density increases, but device complexity increases
Solution Approach 1:
The patent merges multiple capacitor electrodes from different vertical layers and couples them to a single common bitline. This combining of electrodes across layers reduces the total number of separate bitline connections needed, simplifying the overall device architecture. The selective coupling mechanism allows multiple electrodes to share a common access path, reducing device complexity while maintaining the high density benefits of the 3D stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory density and reduces footprint area while maintaining compatibility with advanced CMOS processes, addressing scaling challenges of conventional 1T-1C memory technology.
Implementation Method 1
memory arrays with one access transistor for multiple hysteretic capacitors
Data Source
AI summary
Various arrangements for IC devices implementing memory with one access transistor for multiple hysteretic capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N hysteretic capacitors coupled to the access transistor in a way that allows selecting all of the N hysteretic capacitors for performing READ and/or WRITEs operation when the access transistor is ON. The IC device further includes W wordlines, B bitlines, and P platelines, where N, M, W, B, and P are design variables, each being an integer greater than 1. IC devices implementing memory with one access transistor for multiple hysteretic capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high density embedded memory compatible with advanced CMOS processes.