One-Way Switch Gate Referenced to Back Side Electrode
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Solution Overview
Problem
Existing bidirectional switches exhibit poor dV/dt behavior due to high sensitivity to parasitic thyristor activation, leading to unintended switching during voltage variations.
Innovation Solution
A one-way switch design with its gate referenced to the main back side electrode, featuring a P-type strip connecting a portion of the N-type gate well to the P-type wall, reducing electric resistance and desensitizing the gate contact, combined with a cathode gate thyristor chip to form a bidirectional switch, where the gates and anodes/cathodes are connected to a reference electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate is directly connected to the anode without additional structures, then the device complexity is reduced, but the dV/dt behavior deteriorates due to high sensitivity to parasitic thyristor activation
Solution Approach 1:
The gate structure is segmented into multiple doped regions (P-type gate region 9, N-type gate region 8, P-type strip 12) separated by specific spacing and connected through controlled paths. This segmentation creates distinct functional zones that prevent parasitic thyristor activation while maintaining gate control functionality, directly resolving the contradiction between simplicity and reliability.
Solution Approach 2:
A P-type strip 12 is introduced as an intermediary element connecting the P-type gate well 9 to the P-type wall 7. This intermediary structure provides a controlled electrical path that desensitizes the gate contact to voltage variations, preventing unintended parasitic thyristor turn-on while maintaining necessary electrical connections.
2Speed
If the gate contact is highly sensitive to voltage variations, then the switching response speed is improved, but the reliability deteriorates due to unintended switching during normal voltage fluctuations
Solution Approach 1:
The electrical parameters of the gate structure are modified through specific doping configurations (P-type region 9, N-type region 8, P-type strip 12) and geometric parameters (spacing, dimensions). These parameter changes create a gate structure with optimized sensitivity characteristics that responds appropriately to switching signals while being desensitized to normal voltage fluctuations, resolving the contradiction between speed and reliability.
3Ease of manufacture
If the electric resistance in the gate path is high, then the manufacturing complexity is reduced, but the dV/dt behavior worsens due to increased parasitic thyristor sensitivity
Solution Approach 1:
The P-type strip 12 connects the P-type gate well 9 to the P-type wall 7, creating an equipotential path that equalizes the electrical potential in the gate region. This reduces voltage drops and minimizes the electric field strength that could trigger parasitic thyristor activation, improving dV/dt behavior while maintaining a manufacturable structure using standard doping and metallization processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the dV/dt behavior of both one-way and bidirectional switches by reducing parasitic thyristor sensitivity to overvoltages, ensuring reliable operation and reduced sensitivity to voltage variations.
Implementation Method 1
A P-type strip 12 is formed in the substrate 1 and connects a portion on one side of the well 9 to an upper portion of the wall 7, reducing electric resistance
Data Source
AI summary
A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.