One-Wire Bus Interrupt Debounce With Challenge-Response Validation
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Solution Overview
Problem
Existing serial bus architectures in mobile communication devices face challenges with spurious noise and interference leading to spurious interrupts, which complicate the differentiation between valid and invalid interrupt requests, particularly on one-wire bidirectional buses.
Innovation Solution
Implementing a bus interrupt debounce mechanism using challenge-response sequences and Manchester encoding to distinguish valid interrupts from noise-induced spurious interrupts, followed by an interrupt arbitration process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a one-wire bidirectional bus is used to reduce GPIO pins, then device complexity is reduced, but the bus becomes more susceptible to spurious noise and interference causing false interrupts
Solution Approach 1:
The patent implements a challenge-response mechanism where the host sends challenge pulses and the subordinate device responds with challenge responses. This feedback loop allows verification of legitimate interrupt requests by confirming the subordinate device's ability to respond correctly, thereby distinguishing valid interrupts from spurious noise-induced signals on the one-wire bus.
Solution Approach 2:
The patent performs preliminary debouncing actions before processing interrupt requests. By implementing the challenge-response sequence and arbitration process before accepting interrupts, the system proactively filters out spurious signals and prepares the bus for reliable communication, preventing false interrupts from being processed.
2Productivity
If interrupt requests are processed without debouncing, then processing speed is improved, but false interrupts from noise increase system errors
Solution Approach 1:
The patent applies partial debouncing by implementing a selective challenge-response mechanism that is triggered only when interrupt requests are detected. Rather than continuously debouncing all signals, the system performs verification actions only when needed, balancing processing speed with reliability by applying debouncing selectively to potential interrupt events.
3Reliability
If challenge-response sequences are implemented to filter spurious interrupts, then interrupt accuracy is improved, but communication overhead and processing time increase
Solution Approach 1:
The patent employs periodic challenge pulses sent by the host to the subordinate device as part of the debouncing mechanism. These periodic challenges are timed efficiently to verify interrupt legitimacy without excessive delay, creating a rhythm of verification that balances accuracy with time efficiency in interrupt handling.
Data Source
AI summary
Bus interrupt debounce is described for in band bus interrupts on a one-wire serial bus between a host device and one or more subordinate devices. The host device includes a line driver configured to couple the host device to a one-wire serial bus and a controller. The controller is configured to receive an interrupt request on the one-wire serial bus from a subordinate device coupled to the one-wire serial bus, drive a first sequence of challenge pulses on the one-wire serial bus, receive a second sequence of challenge responses from the subordinate device on the one-wire serial bus in response to the challenge pulses, accept the interrupt request in response to receiving the second sequence of challenge responses, and start an interrupt arbitration for the one-wire serial bus in response to accepting the interrupt request.