One-Wire Bus Interface Using PWM Data Pulses
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Solution Overview
Problem
Digital bus interface designs face challenges in minimizing the number of bus lines due to the increasing complexity and space constraints in modern communication systems, necessitating a reduction in the number of wires and pins required for data, power, and clock signals.
Innovation Solution
A bus interface system utilizing a one wire bus protocol where the master bus controller generates data pulses that include payload, address, and power information, allowing the slave bus controller to decode and verify data without additional bus lines, using pulse width modulation (PWM) to synchronize and power the slave controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional digital bus interface designs are used with separate data, power, and clock bus lines, then reliable data transfer and synchronization are achieved, but the number of bus lines and pins increases, consuming more area
Solution Approach 1:
The patent combines data, power, and clock signals into a single bus line. The master bus controller generates data pulses that simultaneously carry data information and power, while the pulse timing provides synchronization, eliminating the need for separate bus lines for each function.
Solution Approach 2:
The single bus line performs multiple functions: it transmits data, provides power to the slave bus controller, and delivers synchronization timing information. This multi-functional approach replaces traditional separate dedicated lines for each purpose.
2Device complexity
If the number of bus lines is reduced to minimize area, then pin and wire count decreases, but ensuring accurate data reception and error detection becomes more challenging
Solution Approach 1:
The slave bus controller performs error checking on received data pulses and generates an acknowledgment signal back to the master bus controller. This feedback mechanism allows the master to verify successful data reception and request retransmission if errors occur, maintaining high data reception accuracy.
Solution Approach 2:
The master bus controller generates data pulses with built-in error detection capabilities, and the slave bus controller performs error checking before processing the data. This preliminary verification ensures data integrity before further processing occurs.
3Speed
If separate clock bus lines are used for synchronization, then timing accuracy is maintained, but the number of bus lines increases
Solution Approach 1:
The patent merges the clock synchronization function into the data transmission process. The timing and duration of data pulses themselves provide the synchronization signal, eliminating the need for a separate clock bus line.
Solution Approach 2:
The data pulses serve dual purposes: carrying information and providing timing synchronization. The slave bus controller uses the received data pulse timing to synchronize its operations without requiring an external clock signal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of bus lines needed by integrating data, power, and synchronization within a single signal, enhancing efficiency and reducing the physical complexity of the bus interface while maintaining accurate data transfer and error checking.
Implementation Method 1
using pulse width modulation (PWM) to synchronize and power the slave controller
Data Source
AI summary
Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.