One-Wire Bus Interface With PWM Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital bus interfaces face challenges in minimizing the number of bus lines required, leading to increased complexity and pin count, which is particularly problematic in modern communication systems where space is limited.
Innovation Solution
A bus interface system utilizing a one-wire bus protocol where the master bus controller generates data pulses representing commands and error codes, and the slave bus controller decodes these pulses to ensure accurate command execution without additional bus lines for clock or power signals, using a PWM bus protocol to synchronize and power the slave controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional digital bus interfaces are used with separate clock and power lines, then reliable data transmission is achieved, but the number of bus lines and pin count increases
Solution Approach 1:
The patent combines multiple functions (data transmission, clock signaling, and power delivery) into a single bus line. The master controller generates data pulses with varying edge rates that simultaneously carry data information and clock timing, while also providing power to the slave controller through the same line, thereby reducing the total number of required bus lines and pins
Solution Approach 2:
The single bus line performs multiple functions: it transmits data commands from master to slave, provides clock timing signals through controlled edge rates, and delivers power to the slave controller. This multi-functional approach eliminates the need for separate dedicated lines for each function, reducing overall system complexity
2Device complexity
If the number of bus lines is reduced to minimize pin count, then space constraints are addressed, but command execution accuracy may be compromised
Solution Approach 1:
The slave controller includes an error detection mechanism that verifies received commands by checking for expected pulse patterns and edge rate characteristics. When a command is received, the slave validates it against the known protocol requirements (such as expecting specific numbers of rising and falling edges), and only executes verified commands, thereby maintaining high accuracy despite using a reduced number of bus lines
Solution Approach 2:
The master controller generates data pulses with predetermined edge rate characteristics that inherently encode timing and validity information. By pre-shaping the pulses with specific rising and falling edge rates before transmission, the system built-in error prevention mechanisms that allow the slave to distinguish valid commands from noise or corruption, ensuring accurate execution
Data Source
AI summary
Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.