One-Wire Clock Recovery Using Manchester Edge Synchronization
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Solution Overview
Problem
Current serial communication systems face challenges in efficiently managing clock signals over single-wire buses, particularly in mobile communication devices, where phase and frequency errors can lead to data transmission issues and increased demand for GPIO pins due to complex device interactions.
Innovation Solution
A clock and data recovery apparatus that generates a base clock signal and uses a clock gating circuit, counter, and edge synchronization circuit to synchronize clock signals with Manchester-encoded data, enabling robust phase and frequency synchronization without a separate clock line, thus supporting high-speed data transmission over a single-wire bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock line is used for serial communication, then clock synchronization is improved, but the number of GPIO pins required increases
Solution Approach 1:
The patent combines the clock signal and data signal into a single wire by embedding clock information within the Manchester-encoded data signal itself. The edge synchronization circuit detects transitions in the received signal to generate clock cycles, eliminating the need for a separate clock line while maintaining synchronization.
Solution Approach 2:
The single wire serves multiple functions: it carries both data information and clock timing information. The Manchester encoding scheme ensures that every bit transition provides both data value and clock edge information, allowing the same physical medium to perform roles that traditionally required separate channels.
2Use of energy by moving object
If clock gating is implemented to reduce power consumption, then energy efficiency is improved, but clock signal continuity may be affected
Solution Approach 1:
The clock gating circuit enables the oscillator to operate periodically rather than continuously, activating it only during periods when data transmission occurs. The gate control logic responds to signal transitions to temporarily enable clock generation, then disables it during idle periods, reducing power consumption while maintaining clock signal availability when needed.
Solution Approach 2:
The system uses the incoming data signal itself to control the clock gating mechanism. Edges in the received signal automatically trigger clock cycles through the edge synchronization circuit, which in turn controls the gating of the local oscillator, creating a self-regulating system that adapts to data transmission requirements without external control.
Data Source
AI summary
A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.