One-Wire Bus Clock Recovery with Edge-Synchronized Gating
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Solution Overview
Problem
Existing mobile communication devices face challenges in achieving high-speed data transmission over single-wire serial buses due to phase and frequency errors, which conventional clock generation circuits are unable to address effectively, leading to limited data rates and increased power consumption.
Innovation Solution
A clock and data recovery apparatus that generates a base clock signal and synchronizes it with Manchester-encoded signals, using a clock gating circuit and edge synchronization to maintain synchronization and prevent error accumulation, enabling high-speed data transmission over a single-wire bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR circuits are used in high-speed one-wire bidirectional bus, then data recovery can be achieved, but power consumption increases and latency is introduced
Solution Approach 1:
The patent extracts the essential function of clock and data recovery by directly sampling the incoming data signal at its peak amplitude points without using a separate CDR circuit. This removes the power-consuming CDR circuit while maintaining data recovery capability through clever sampling timing controlled by a simplified clock generator.
Solution Approach 2:
The system uses the incoming data signal itself to determine sampling points by detecting peak amplitude points. The data signal provides its own timing information, eliminating the need for an external CDR circuit to generate sampling clocks, thereby reducing power consumption while maintaining reliable data recovery.
2Reliability
If conventional CDR circuits are used in high-speed one-wire bidirectional bus, then data recovery can be achieved, but processing latency increases
Solution Approach 1:
The patent removes the latency-introducing CDR circuit and replaces it with direct sampling at peak amplitude points. This extraction of the CDR function eliminates the processing pipeline stages and buffering required in conventional CDR, thereby reducing processing latency while maintaining data recovery reliability.
Solution Approach 2:
The system performs preliminary action by pre-sampling the data signal at peak amplitude points before further processing. This advance sampling at optimally timed points ensures that data is captured at the best moment without requiring subsequent complex recovery operations, thereby reducing overall processing latency.
3Use of energy by moving object
If peak amplitude point sampling is used, then power consumption is reduced and latency is minimized, but precise timing control is required
Solution Approach 1:
The clock generator serves multiple functions: it generates the sampling clock, detects peak amplitude points, and controls the timing of data sampling all through a single unified mechanism. This multi-functionality reduces the need for separate complex timing control circuits while maintaining precise sampling timing, thereby reducing power consumption without proportionally increasing complexity.
Data Source
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AI summary
A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.