One-Wire Non-Volatile Memory With Dual-Clock State Machines
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Solution Overview
Problem
Existing non-volatile memory devices with one-wire interfaces face challenges in achieving high performance in terms of efficiency and error handling, particularly due to the need for improved communication protocols and data integrity.
Innovation Solution
A dual-state machine system driven by different clocks, utilizing a one-wire communication interface with an interface controller, internal clock oscillator, and separate state machines to process bit and byte information, ensuring reliable data transmission and error handling through specific operational states and counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a one-wire interface is used to reduce pin count, then device complexity and cost are reduced, but communication efficiency and error handling performance deteriorate
Solution Approach 1:
The communication interface is segmented into two separate state machines: a first state machine for byte-level processing and a second state machine for bit-level processing. This segmentation allows each state machine to specialize in specific communication tasks, improving overall communication efficiency while maintaining the one-wire interface's low pin count advantage.
Solution Approach 2:
The system dynamically switches between different operational states (idle, command, address, wait, read, write, high voltage) based on the communication phase. The state machines adapt their behavior dynamically to handle different communication requirements, enabling efficient data transmission and robust error handling within the constrained one-wire interface.
2Ease of operation
If a one-wire interface is used to simplify power management, then ease of operation is improved, but communication reliability deteriorates
Solution Approach 1:
The system incorporates a high voltage state that applies elevated voltage levels before critical write operations to ensure reliable data programming. This beforehand cushioning approach compensates for the potential reliability issues of the one-wire interface by proactively strengthening the signal during vulnerable operation phases.
Solution Approach 2:
The state machines implement feedback mechanisms to monitor communication status and detect errors. When errors are detected or communication phases are completed, the system transitions between states accordingly, ensuring reliable operation while maintaining the simplified power management benefits of the one-wire interface.
Data Source
AI summary
A system and method for one-wire non-volatile memory are provided. The system comprises a one-wire communication interface coupled with a single-wire serial bus and a non-volatile memory to process data communication according to one-wire communication protocol. The one-wire communication interface comprises an interface controller, an internal clock oscillator, a first and a second state machine. The second state machine is driven by a first clock signal generated by the internal clock oscillator and is configured to process bit signal communicated on the serial bus via the interface controller. The first state machine is coupled to the second state machine, and is driven by a second clock signal defined by the falling edge of the data signal on the serial bus. The first state machine is configured to process byte information received from the second state machine.