One-Wire Power IC Communication Using Pulse-Width Decoding

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Solution Overview

Problem

Current communication protocols in power converters require multiple external pins for data and clock signals, which is inefficient for integrated circuits with limited pin availability.

Innovation Solution

A one wire communication protocol using a single external pin to generate internal data and clock signals by comparing pulse width of input signals to predetermined thresholds, enabling communication between integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple external pins are used for data and clock signals, then communication reliability is improved, but device complexity and pin count increase

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidpin count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple communication functions (data transmission and clock signaling) into a single communication pin. The phase circuit compares the input pulse signal width to generate both data and clock signals internally, eliminating the need for separate SDA and SCL pins while maintaining communication reliability through pulse width modulation encoding

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single communication pin performs multiple functions: it carries both data information and clock timing signals. The phase circuit enables this multi-functionality by extracting both data and clock components from the same input signal, allowing one pin to replace traditional two-pin I2C communication

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Volume of moving object

If integration of power ICs is increased, then device size is reduced, but pin availability decreases

Engineering Contradiction:
Improvedevice sizeVSAvoidpin availability
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

By merging data and clock functions into a single pin interface, the patent reduces the number of external connections required. This enables higher integration density in power ICs as fewer pins are needed for communication, allowing more functionality to be integrated within the same package footprint

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from spatial separation of data and clock pins to temporal multiplexing within a single pin. By encoding information in pulse width dimensions rather than requiring separate physical channels, the system achieves higher integration without sacrificing communication capability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250373145A1Circuits and methods for one wire communication protocol
Publication Date: 2025.12.04 NAVITAS SEMICON LTD
  • US20250373145A1 patent drawing
  • US20250373145A1 patent drawing
  • US20250373145A1 patent drawing

AI summary

A one wire communication protocol for a power supply system is disclosed. In one aspect, a power supply system includes a controller circuit including an output pin, the controller circuit being arranged to transmit a pulse signal having a pulse width at the output pin, a phase circuit including an input pin, a bus connecting the output pin to the input pin, where the phase circuit is arranged to compare the pulse width of the pulse signal to a predetermined threshold and generate a corresponding data signal based on the comparison.