One-Side Gate Stack FinFET for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional FinFETs suffer from the short channel effect and high parasitic capacitance, leading to low switching speed and increased power consumption due to capacitive coupling between the source/drain regions and the gate, limiting the reduction of both parasitic resistance and capacitance.
Innovation Solution
A semiconductor device with a semiconductor fin on an SOI substrate, featuring a gate stack that extends only from one side of the fin, eliminating capacitive coupling between the source/drain regions and the gate, and incorporating stressors to enhance charge carrier mobility, allowing for a reduced channel region thickness and increased switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate is provided between and extends parallel to source/drain regions in a conventional FinFET, then the device structure is simple and easy to manufacture, but capacitive coupling is introduced between the source/drain region and the gate, resulting in large parasitic capacitance
Solution Approach 1:
The gate is extracted from its conventional position between the source and drain regions and relocated to extend only from one side of the fin. This extraction eliminates the capacitive coupling between the gate and source/drain regions, thereby removing the harmful parasitic capacitance while preserving the essential gate control function over the channel region
Solution Approach 2:
The gate structure transitions from a planar configuration extending between source and drain to a side-extended configuration that runs parallel to the fin length. This dimensional repositioning changes the spatial relationship between gate and source/drain regions, eliminating overlap and capacitive coupling while maintaining channel control through the side-extended geometry
2Reliability
If the channel region thickness is reduced to suppress the short channel effect, then the short channel effect is suppressed and gate control is improved, but the device requires more precise manufacturing control
Solution Approach 1:
The side-extended gate structure is formed in advance to establish precise alignment references before channel region formation. This preliminary positioning of the gate structure enables self-aligned processes that define the channel thickness with high precision, reducing the impact of manufacturing variations on the final device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses the short channel effect, reduces parasitic capacitance and resistance, and enhances charge carrier mobility, resulting in increased access speed and reduced power consumption for non-volatile memory applications.
Implementation Method 1
a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region
Implementation Method 2
incorporating stressors to enhance charge carrier mobility
Data Source
AI summary
The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET.