One-Wire ECDD Signal Modulation for Skew Elimination
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Solution Overview
Problem
Existing digital data communication systems require two electrical paths for data and clock signals, leading to high costs, resource-intensive manufacturing, and skew issues due to differing signal arrival times, which complicates data latching and increases the risk of errors, especially at high clock rates.
Innovation Solution
Combining data and clock signals into a single electrical signal using a direct period synthesizer, where pulse edges function as clock signals and pulse duty cycles represent digital values, reducing the number of necessary electrical paths and eliminating skew by creating an ECDD signal for one-wire communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate electrical paths are used for data and clock signals, then data communication reliability is maintained through synchronized timing, but manufacturing cost and system size increase significantly
Solution Approach 1:
The patent combines data and clock signals into a single electrical path by encoding the clock signal within the data signal waveform. The transmitter modulates the data signal with the clock signal, and the receiver extracts both signals from the same physical channel, eliminating the need for separate data and clock wires while maintaining synchronization through the embedded clock information.
2Reliability
If two separate electrical paths are used for data and clock signals, then timing synchronization is maintained, but manufacturing cost and physical area increase
Solution Approach 1:
The patent merges data and clock signals into one physical channel, reducing the physical area required for signal transmission. By encoding clock information within the data signal waveform through modulation techniques, the system eliminates redundant physical paths while preserving timing synchronization through the embedded clock signal.
3Ease of manufacture
If separate electrical paths are used for data and clock, then signal transmission is simplified, but skew between data and clock signals occurs causing latching errors
Solution Approach 1:
The patent eliminates skew between data and clock signals by combining them into a single electrical path. The clock signal is embedded within the data signal waveform through modulation, ensuring that both signals traverse the same physical medium and arrive simultaneously at the receiver, thereby eliminating timing skew and latching errors.
4Productivity
If multiple data paths are accompanied by one clock path, then resource utilization improves, but delay optimization becomes difficult due to unpredictable skew
Solution Approach 1:
The patent applies the merging principle to each data path individually, embedding its own clock signal within the data waveform. This allows multiple data paths to be transmitted efficiently while each path maintains independent timing synchronization through its embedded clock, eliminating the skew optimization problems associated with shared clock paths.
Data Source
AI summary
A one-wire communication bus for transferring a sequence of digital data from a transmitter to a receiver includes (a) an ECDD signal modulation circuit to create an electrical pulse train wherein each pulse's edge is used as clock signal and each pulse's duty cycle is used to represent digital value of zero and one; (b) an ECDD signal demodulation circuit to receive the ECDD pulse train using a group of sampling cells and to decode the sampled results using a majority voting circuit; (c) an electrical connection between a transmitter wherein the ECDD signal modulation circuit resides and a receiver wherein the ECDD signal demodulation circuit resides. Said ECDD signal is sent from the transmitter to the receiver through the electrical connection. Methods of creating the ECDD pulse train in the transmitter and decoding the ECDD pulse train in the receiver are also disclosed.